A New Gas Bio-Sensor in the Structure of a Micro-Machined Clamped-Clamped Inertial Beam and its Readout Circuit

2012 ◽  
Author(s):  
Bing-Ze Xue ◽  
Paul C.-P. Chao ◽  
Bor-Shyh Lin ◽  
Chun-Yin Tsai ◽  
Tsung-Lin Chen ◽  
...  
Keyword(s):  
Phase Difference ◽  
Reference Signal ◽  
Wheatstone Bridge ◽  
Phase Detector ◽  
Instrumentation Amplifier ◽  
Readout Circuit ◽  
Square Wave ◽  
On Chip ◽  
Bridge Circuits ◽  
Wave Conversion

This study presents a novel gas bio-sensor in the form of a micro-machined resonator and its readout circuit. The resonator has the structure of a clamped-clamped beam with thermal actuation and piezo-resistive sensing that supports a plate capable of being attached with test gas molecules to detect gas concentration. The purpose of this study is to design and fabricate the micro-scaled inertial beam with its readout circuit in a system-on-chip package. The circuit includes a driver, a front-end converter, a feed-trough reduction unit, a square-wave converter and a phase detector. In the process of signal reading, the sensor is first driven by a DDS module and power amplifier, and then sense the vibrations by piezo-resistivity. The piezo-resistivity is detected by a Wheatstone bridge circuits. The carried signal of modulation is processed by a Wheatstone bridge circuits. An instrumentation amplifier adjusts the gain to the appropriate amplitude. The circuit with reduction on feed-through noise increases the SNR. Square wave conversion circuit and PFD process the signal and the driver reference signal to detect phase difference. The data of phase difference is counted into a microcontroller dsPIC4011 and then the data being transmitted to the computer by RS232 to a USB adapter. Finally, the whole circuit is implemented by using TSMC 0.35 2P4M process and one-step postprocessing.

A Mixed-Voltage Sensor Readout Circuit With On-Chip Calibration and Built-In Self-Test

2007 ◽  
Vol 7 (9) ◽  
pp. 1225-1232 ◽  
Author(s):  
Andrew Mason ◽  
Abhijeet V. Chavan ◽  
Kensall D. Wise
Keyword(s):  
Voltage Sensor ◽  
Readout Circuit ◽  
Self Test ◽  
Built In Self Test ◽  
On Chip

On-Chip Touch Sensor Readout Circuit Using Passive Sigma-Delta Modulator Capacitance-to-Digital Converter

2015 ◽  
Vol 15 (7) ◽  
pp. 3893-3902 ◽  
Author(s):  
Bo Liu ◽  
Zaniar Hoseini ◽  
Kye-Shin Lee ◽  
Yong-Min Lee
Keyword(s):  
Readout Circuit ◽  
Digital Converter ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Touch Sensor ◽  
On Chip

scholarly journals Ultracompact on-chip photothermal power monitor based on silicon hybrid plasmonic waveguides

Nanophotonics ◽  
2017 ◽  
Vol 6 (5) ◽  
pp. 1121-1131 ◽  
Author(s):  
Hao Wu ◽  
Ke Ma ◽  
Yaocheng Shi ◽  
Lech Wosinski ◽  
Daoxin Dai
Keyword(s):  
Silicon Oxide ◽  
Dynamic Range ◽  
Optical Power ◽  
Wheatstone Bridge ◽  
Response Speed ◽  
Electrical Signal ◽  
Metal Strip ◽  
Plasmonic Waveguides ◽  
Insulator Layer ◽  
On Chip

AbstractWe propose and demonstrate an ultracompact on-chip photothermal power monitor based on a silicon hybrid plasmonic waveguide (HPWG), which consists of a metal strip, a silicon core, and a silicon oxide (SiO2) insulator layer between them. When light injected to an HPWG is absorbed by the metal strip, the temperature increases and the resistance of the metal strip changes accordingly due to the photothermal and thermal resistance effects of the metal. Therefore, the optical power variation can be monitored by measuring the resistance of the metal strip on the HPWG. To obtain the electrical signal for the resistance measurement conveniently, a Wheatstone bridge circuit is monolithically integrated with the HPWG on the same chip. As the HPWG has nanoscale light confinement, the present power monitor is as short as ~3 μm, which is the smallest photothermal power monitor reported until now. The compactness helps to improve the thermal efficiency and the response speed. For the present power monitor fabricated with simple fabrication processes, the measured responsivity is as high as about 17.7 mV/mW at a bias voltage of 2 V and the power dynamic range is as large as 35 dB.

scholarly journals A 24.88 nV/√Hz Wheatstone Bridge Readout Integrated Circuit with Chopper-Stabilized Multipath Operational Amplifier

2020 ◽  
Vol 10 (1) ◽  
pp. 399 ◽  
Author(s):  
Kwonsang Han ◽  
Hyungseup Kim ◽  
Jaesung Kim ◽  
Donggeun You ◽  
Hyunwoo Heo ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Operational Amplifier ◽  
Wheatstone Bridge ◽  
Input Resistance ◽  
Cmos Technology ◽  
Low Noise ◽  
Oxide Semiconductor ◽  
Instrumentation Amplifier ◽  
Readout Integrated Circuit ◽  
Chopper Stabilization

This paper proposes a low noise readout integrated circuit (IC) with a chopper-stabilized multipath operational amplifier suitable for a Wheatstone bridge sensor. The input voltage of the readout IC changes due to a change in input resistance, and is efficiently amplified using a three-operational amplifier instrumentation amplifier (IA) structure with high input impedance and adjustable gain. Furthermore, a chopper-stabilized multipath structure is applied to the operational amplifier, and a ripple reduction loop (RRL) in the low frequency path (LFP) is employed to attenuate the ripple generated by the chopper stabilization technique. A 12-bit successive approximation register (SAR) analog-to-digital converter (ADC) is employed to convert the output voltage of the three-operational amplifier IA into digital code. The Wheatstone bridge readout IC is manufactured using a standard 0.18 µm complementary metal-oxide-semiconductor (CMOS) technology, drawing 833 µA current from a 1.8 V supply. The input range and the input referred noise are ±20 mV and 24.88 nV/√Hz, respectively.

First integrated inductive proximity sensor with on-chip CMOS readout circuit and electrodeposited 1 mm flat coil

1999 ◽  
Vol 76 (1-3) ◽  
pp. 273-278 ◽  
Author(s):  
Ph.A. Passeraub ◽  
P.-A. Besse ◽  
A. Bayadroun ◽  
S. Hediger ◽  
E. Bernasconi ◽  
...  
Keyword(s):  
Readout Circuit ◽  
Proximity Sensor ◽  
On Chip

scholarly journals Design of an All-Digital Synchronized Frequency Multiplier Based on a Dual-Loop (D/FLL) Architecture

VLSI Design ◽  
2012 ◽  
Vol 2012 ◽  
pp. 1-7 ◽  
Author(s):  
Maher Assaad ◽  
Mohammed H. Alser
Keyword(s):  
Integrated Circuit ◽  
Reference Signal ◽  
Digital Processing ◽  
System On Chip ◽  
Frequency Multiplier ◽  
Experimental Results ◽  
Clock Signal ◽  
Phase Tracking ◽  
Frequency Locked Loops ◽  
On Chip

This paper presents a new architecture for a synchronized frequency multiplier circuit. The proposed architecture is an all-digital dual-loop delay- and frequency-locked loops circuit, which has several advantages, namely, it does not have the jitter accumulation issue that is normally encountered in PLL and can be adapted easily for different FPGA families as well as implemented as an integrated circuit. Moreover, it can be used in supplying a clock reference for distributed digital processing systems as well as intra/interchip communication in system-on-chip (SoC). The proposed architecture is designed using the Verilog language and synthesized for the Altera DE2-70 development board. The experimental results validate the expected phase tracking as well as the synthesizing properties. For the measurement and validation purpose, an input reference signal in the range of 1.94–2.62 MHz was injected; the generated clock signal has a higher frequency, and it is in the range of 124.2–167.9 MHz with a frequency step (i.e., resolution) of 0.168 MHz. The synthesized design requires 330 logic elements using the above Altera board.

scholarly journals A One-Dimensional Magnetic Chip with a Hybrid Magnetosensor and a Readout Circuit

2018 ◽  
Vol 2018 ◽  
pp. 1-10
Author(s):  
Guo-Ming Sung ◽  
Hsin-Kwang Wang ◽  
Leenendra Chowdary Gunnam
Keyword(s):  
Field Effect Transistors ◽  
Oxide Semiconductor ◽  
Instrumentation Amplifier ◽  
Maximum Output ◽  
Hall Voltage ◽  
Readout Circuit ◽  
Pass Filter ◽  
Low Pass Filter ◽  
One Dimensional ◽  
Macro Model

This work presents a one-dimensional magnetic chip composed of a hybrid magnetosensor and a readout circuit, which were fabricated with 0.18 μm 1P6M CMOS technology. The proposed magnetosensor includes a polysilicon cross-shaped Hall plate and two separated metal-oxide semiconductor field-effect transistors (MOSFETs) to sense the magnetic induction perpendicular to the chip surface. The readout circuit, which comprises a current-to-voltage converter, a low-pass filter, and an instrumentation amplifier, is designed to amplify the output Hall voltage with a gain of 43 dB. Furthermore, a SPICE macro model is proposed to predict the sensor’s performance in advance and to ensure sufficient comprehension of the magnetic mechanism of the proposed magnetosensor. Both simulated and measured results verify the correctness and flexibility of the proposed SPICE macro model. Measurements reveal that the maximum output Hall voltage VH, the optimum current-related magnetosensitivity SRI, the optimum voltage-related magnetosensitivity SRV, the averaged nonlinearity error NLE, and the relative bias current Ibias are 4.381 mV, 520.5 V/A·T, 40.04 V/V·T, 7.19%, and 200 μA, respectively, for the proposed 1-D magnetic chip with a readout circuit of 43 dB. The averaged NLE is small at high magnetic inductions of ±30 mT, whereas it is large at low magnetic inductions of ±30 G.

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