Stabilization of Electrostatic Actuators Through Variable Gain Amplifier

Author(s):  
Sangtak Park ◽  
Eihab Abdel-Rahman

In the presence of high parasitic capacitance, conventional electrostatic actuation methods fail to drive an electrostatic actuator beyond its pull-in point. Although the resonant drive circuit is able to extend the operation range of an electrostatic actuator further at a much lower input voltage, an electrostatic actuator coupled with the resonant drive circuit also undergoes pull-in in the presence of high parasitic capacitance compared to the circuit’s quality factor. To improve its robustness to high parasitic capacitance, we design a variable gain amplifier that reduces voltage gain as an electrostatic actuator moves towards its bottom electrode: the increase in the impedance of the resonant drive circuit reduces voltage gain of a variable gain amplifier through its positive feedback loop, while its negative feedback stabilizes its operation.

Author(s):  
Sangtak Park ◽  
Eihab Abdel-Rahman

Most electrostatic actuators fabricated by MEMS technology require high actuation voltage and suffer from the pull-in phenomenon that limits the operation range. We present an amplitude-modulated resonant drive circuit to drive electrostatic actuators at much lower supply voltage than that of conventional actuators to extend their operation range. Analytical and numerical models facilitate stability analysis of electrostatic actuators coupled with the resonant drive circuit. We study the impact of parasitic capacitance and the quality factor of the resonant drive circuit on the operation range of electrostatic actuators. Furthermore, we present a new method to measure the displacement of electrostatic actuators by sensing the phase delay of the actuation voltage with respect to the input voltage. This measurement method allows us to easily incorporate feedback control into existing electrostatic actuators without any modification to the actuator itself.


2017 ◽  
Vol 26 (08) ◽  
pp. 1740003 ◽  
Author(s):  
Daniel Arbet ◽  
Viera Stopjaková ◽  
Martin Kováč ◽  
Lukáš Nagy ◽  
Matej Rakús ◽  
...  

In this paper, a variable gain amplifier (VGA) designed in 130 nm CMOS technology is presented. The proposed amplifier is based on the bulk-driven (BD) design approach, which brings a possibility to operate with low supply voltage. Since the supply voltage of only 0.6 V is used for the amplifier to operate, there is no risk of latch-up event that usually represents the main drawback of the BD circuit systems. BD transistors are employed in the input differential stage, which makes it possible to operate in rail-to-rail input voltage range. Achieved simulation results indicate that gain of the proposed VGA can be varied in a wide scale, which together with the low supply voltage feature make the proposed amplifier useful for low-voltage and low-power applications. An additional circuit responsible for maintaining the linear-in-decibel gain dependency of the VGA is also addressed. The proposed circuit block avails arbitrary shaping of the curve characterizing the gain versus the controlling voltage dependency.


This paper presents design of a sampler circuit for folding flash ADC. There is a desire for Low power high performance ADC for communication. For low power the size of the ADC should be minimized and for the fast performance flash can be used. Hence to reduce the number of transistors in flash ADC folding network is proposed here. Sampling is the important technique used in the ADC part. In this discussion the sampler circuit includes a differential track and hold switch followed by a variable gain amplifier with a gain of 1 db, a buffer and a folding network. An input voltage of1 V and the sampling frequency of 1GS/s is applied to the sampler circuit. Effective number of bits of more than 5.7 bits is achieved also THD is below -35db in VGA. Buffer achieves a ENOB of 10bits with THD less than -65db. This sampler circuit is designed with the technology of 45nm for coherent sampling. Worst case SNDR is calculated.


2009 ◽  
Vol 129 (10) ◽  
pp. 1968-1969
Author(s):  
Tetsuro Okura ◽  
Shunsuke Okura ◽  
Toru Ido ◽  
Kenji Taniguchi

Author(s):  
Jorge Pérez Bailón ◽  
Jaime Ramírez-Angulo ◽  
Belén Calvo ◽  
Nicolás Medrano

This paper presents a Variable Gain Amplifier (VGA) designed in a 0.18 μm CMOS process to operate in an impedance sensing interface. Based on a transconductance-transimpedance (TC-TI) approach with intermediate analog-controlled current steering, it exhibits a gain ranging from 5 dB to 38 dB with a constant bandwidth around 318 kHz, a power consumption of 15.5 μW at a 1.8 V supply and an active area of 0.021 mm2.


Electronics ◽  
2021 ◽  
Vol 10 (7) ◽  
pp. 804
Author(s):  
Gibeom Shin ◽  
Kyunghwan Kim ◽  
Kangseop Lee ◽  
Hyun-Hak Jeong ◽  
Ho-Jin Song

This paper presents a variable-gain amplifier (VGA) in the 68–78 GHz range. To reduce DC power consumption, the drain voltage was set to 0.5 V with competitive performance in the gain and the noise figure. High-Q shunt capacitors were employed at the gate terminal of the core transistors to move input matching points for easy matching with a compact transformer. The four stages amplifier fabricated in 40-nm bulk complementary metal oxide semiconductor (CMOS) showed a peak gain of 24.5 dB at 71.3 GHz and 3‑dB bandwidth of more than 10 GHz in 68–78 GHz range with approximately 4.8-mW power consumption per stage. Gate-bias control of the second stage in which feedback capacitances were neutralized with cross-coupled capacitors allowed us to vary the gain by around 21 dB in the operating frequency band. The noise figure was estimated to be better than 5.9 dB in the operating frequency band from the full electromagnetic (EM) simulation.


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