Polyimide Multi-Layer Substrate for High-Density Semiconductor Package

2005 ◽  
Author(s):  
Shoichi Takenaka ◽  
Shoji Ito ◽  
Ryoichi Kishihara ◽  
Masahiro Okamoto ◽  
Osamu Nakao
Keyword(s):  
Conventional Method ◽  
Polyimide Film ◽  
High Density ◽  
Electrical Connection ◽  
Via Holes

We have developed a polyimide multi-layer substrate for semiconductor package. Interstitial via holes filled with conductive paste make the electrical connection in any layers in the multi-layer substrate to realize high-density wiring. The substrate shows reliable resistance to moisture and heat. Use of polyimide film make the substrate considerable thin compared to the conventional method using glass-epoxy. The present multi-layer substrate can be applied to a promising interposer for high-density semiconductor such as multi-chip module and stacked chip.

High-Density Through-Wafer Electrical Interconnects in Pyrex Substrate Integrated With Micromirror Array

2003 ◽  
Author(s):  
C. C. Wang ◽  
T. D. Kudrle ◽  
M. Bancu ◽  
J. Hsiao ◽  
C. H. Mastrangelo
Keyword(s):  
Flip Chip ◽  
High Density ◽  
Anodic Bonding ◽  
Thermal Coefficient ◽  
Electrical Interconnects ◽  
Via Holes ◽  
Multiple Levels ◽  
Micromirror Array

A method for the construction of high density (2.4 mm−2) vertical leads through a pyrex substrate is presented. The pyrex substrate behaves as a TCE (Thermal Coefficient of Expansion) matched interposer that permits anodic bonding of silicon micromirrors on one side and flip-chip bumping of multiplexing electronic chips on its opposite side. Electrical leads consist of 250±25 μm-diameter holes formed by AJM machining and coated with evaporated Au yielding via resistances of 0.5–0.7 Ω. The via holes are sealed with a new spin-cast polyimide tenting process that enables the subsequent patterning of multiple levels of metal using conventional lithographic techniques.

Rapid treatment of polyimide film surfaces using high-density microwave plasma for enhancement of Cu layer adhesion

Vacuum ◽  
2008 ◽  
Vol 83 (3) ◽  
pp. 501-505 ◽  
Author(s):  
Y. Takagi ◽  
Y. Gunjo ◽  
H. Toyoda ◽  
H. Sugai
Keyword(s):  
Microwave Plasma ◽  
Polyimide Film ◽  
High Density ◽  
Rapid Treatment

scholarly journals Quality Assurance of via Holes in the Wiring Board with High Density Conductive Pattern

2015 ◽  
Vol 4 ◽  
pp. 87-91
Author(s):  
Z.A. Mironova ◽  
◽  
D.D. Kariagina ◽  
B.V. Vladimirov ◽  
A.V. Pavlov ◽  
...  
Keyword(s):  
Quality Assurance ◽  
High Density ◽  
Conductive Pattern ◽  
Via Holes ◽  
Wiring Board

Flexible Circuit Board Package Embedded With Multi-Stack Dies

2020 ◽  
Author(s):  
Nobuki Ueta ◽  
Shunsuke Sato ◽  
Masakazu Sato ◽  
Yoshio Nakao ◽  
Joshua Magnuson ◽  
...  
Keyword(s):  
Hearing Aids ◽  
High Reliability ◽  
Polyimide Film ◽  
High Density ◽  
Circuit Board ◽  
Electrical Measurements ◽  
Test Vehicle ◽  
One Step ◽  
Lamination Process ◽  
High Density Packaging

Abstract Miniaturization of electronics modules is always required for various medical applications including wearable technology, such as hearing aids, and implantable devices. Many types of high-density packaging technologies, such as package-on-package, bare-die stack, flex folded package and Through Si Via (TSV) technologies, have been proposed and used to fulfill the request. Among them, embedded die technology is one of the promising technologies to realize miniaturization and high-density packaging. We have developed WABE™ (wafer and board level device embedded) technology for embedding dies into multilayer flexible printed circuit (FPC) boards. The WABE package is comprised of thin dies (85 μm thickness), multi-layer polyimide, adhesive films and conductive paste. The dies are sandwiched by polyimide films with Cu circuits (FPCs). The conductive paste provides electrical connections between the layers as well as the layer and embedded die. First, each FPC layer is fabricated individually, and via holes are filled with conductive paste, and the dies are mounted on certain layers. Then, all layers undergo a one-step co-lamination process, and they are pressed to cure the adhesive material and conductive paste at the same time. This WABE technology has enabled multiple dies to be embedded by the one-step lamination process. Even if multiple dies are embedded, the footprint of a package can be reduced drastically by embedding multiple dies vertically in stacks. This paper describes the details of the results of fabricating a test vehicle with six embedded dies (three-dies in two stacks side-by-side). The fabricated test vehicle had 14 copper layers with less than 0.9 mm thickness. This paper also reports the results of various reliability testing on the package. These results were obtained by electrical measurements of daisy chain patterns formed between some of the layers. The fabricated test vehicle showed high reliability based on the results of a moisture and heat test and heat-shock test. These results show that the WABE technology to embed multiple dies vertically in polyimide film is one of the most promising packaging technologies to significantly miniaturize electronic circuits such as medical electronics.

Development of High Reliability Via on IVH (VONI) for High Density Interconnect Circuit Boards

2007 ◽  
Vol 4 (2) ◽  
pp. 78-85
Author(s):  
Jong-Won Park ◽  
Yun-Seok Hwang ◽  
Il-Kyoon Jeun ◽  
Da-Hee Joung ◽  
Myung-Gun Chong ◽  
...  
Keyword(s):  
Water Adsorption ◽  
High Reliability ◽  
Chemical Properties ◽  
High Density ◽  
Circuit Boards ◽  
Shock Testing ◽  
Via Holes ◽  
Via Hole ◽  
The Relationship ◽  
High Density Packaging

Via on interstitial via hole (VONI) technique is a complex set of technologies for blind and buried vias in traditional sequential lamination cycles with external layers, and micro via holes (MVH) for true high-density packaging. However, when VONI is repeatedly subjected to thermal stress, the interstitial via hole (IVH) in its structure often creates problems such as IVH barrel cracks, and layer-layer delamination. To solve VONI's reliability problems, such as IVH barrel crack and layer-layer delamination, the authors have investigated the relationship between the CTE difference and the effect of moisture. Through using different types of plugging inks, it was clearly indicated that delamination was related to the chemical properties of the plugging inks. For example delamination was dominated by the inks property of water adsorption, which induced vapor pressure when it undergoes thermal shock testing. The authors have solved the delamination problem by reducing the ratio of water adsorption in the plugging ink.

Generation of Blind Via-Holes for a High Density Multi-Chip-Module Using Excimer Lasers

1989 ◽  
Vol 158 ◽  
Author(s):  
Friedrich G. Bachmann
Keyword(s):  
Large Scale ◽  
Printed Circuit Board ◽  
High Density ◽  
Circuit Board ◽  
Excimer Lasers ◽  
Signal Delay ◽  
Delay Times ◽  
Via Holes ◽  
On Chip ◽  
First Time

ABSTRACTIn recent years the on-chip delay has gone down much more rapidly than the signal delay in packaged circuits. As a consequence of this the packaging delay times have had to be reduced drastically, which means that a greater packging density had to be implemented. A novel planar packaging technique, used in the new Siemens main frame computer 7500 H 90 has led to considerable progress in solving this problem. An essential part of this system is a multi-chip-module which can hold up to 144 bare chips. The carrier of these IC's is a 16-layer high density multilayer printed circuit board, which is fabricated in a sequential process. Interlayer contacts are formed by 80 µm wide blind via-holes, which are generated by excimer-laser ablation of the dielectric. The process desribed in this paper shows that it is possible to produce blind via-holes with an aspect ratio of about one in an extremely reliable and reproducible way. This process is already being successfully run on a production line. It is to our best knowledge the first time excimer lasers have been used on a large-scale in an industrial environment.

Planar defects in ordered (Ga,In)P

1988 ◽  
Vol 46 ◽  
pp. 902-903
Author(s):  
S. McKernan ◽  
C. B. Carter ◽  
D. Bour ◽  
J. R. Shealy
Keyword(s):  
Electron Diffraction ◽  
Vapor Phase ◽  
Growth Direction ◽  
High Density ◽  
Ordered Structure ◽  
Planar Defects ◽  
Diffraction Patterns ◽  
Ternary Semiconductors ◽  
Anion Species ◽  
Metallic Vapor

The growth of ternary III-V semiconductors by organo-metallic vapor phase epitaxy (OMVPE) is widely practiced. It has been generally assumed that the resulting structure is the same as that of the corresponding binary semiconductors, but with the two different cation or anion species randomly distributed on their appropriate sublattice sites. Recently several different ternary semiconductors including AlxGa1-xAs, Gaxln-1-xAs and Gaxln1-xP1-6 have been observed in ordered states. A common feature of these ordered compounds is that they contain a relatively high density of defects. This is evident in electron diffraction patterns from these materials where streaks, which are typically parallel to the growth direction, are associated with the extra reflections arising from the ordering. However, where the (Ga,ln)P epilayer is reasonably well ordered the streaking is extremely faint, and the intensity of the ordered spot at 1/2(111) is much greater than that at 1/2(111). In these cases it is possible to image relatively clearly many of the defects found in the ordered structure.

Quantitative defect studies in semiconductor TEM samples prepared by low angle ion milling

1995 ◽  
Vol 53 ◽  
pp. 512-513
Author(s):  
L. Mulestagno ◽  
J.C. Holzer ◽  
P. Fraundorf
Keyword(s):  
Sample Preparation ◽  
Milling Time ◽  
High Density ◽  
Low Density ◽  
Ion Milling ◽  
High Quality ◽  
Variable Angle ◽  
Major Disadvantage ◽  
Induced Defects

Due to the wealth of information, both analytical and structural that can be obtained from it TEM always has been a favorite tool for the analysis of process-induced defects in semiconductor wafers. The only major disadvantage has always been, that the volume under study in the TEM is relatively small, making it difficult to locate low density defects, and sample preparation is a somewhat lengthy procedure. This problem has been somewhat alleviated by the availability of efficient low angle milling.Using a PIPS® variable angle ion -mill, manufactured by Gatan, we have been consistently obtaining planar specimens with a high quality thin area in excess of 5 × 104 μm2 in about half an hour (milling time), which has made it possible to locate defects at lower densities, or, for defects of relatively high density, obtain information which is statistically more significant (table 1).

Using the scanning electron microscope for failure analysis of high density magnetic media

1987 ◽  
Vol 45 ◽  
pp. 392-393
Author(s):  
Evelyn R. Ackerman ◽  
Gary D. Burnett
Keyword(s):  
Electron Microscope ◽  
Scanning Electron Microscope ◽  
Failure Analysis ◽  
High Density ◽  
Magnetic Media ◽  
Specific Data ◽  
Retrieval Systems ◽  
Operating Environments ◽  
The Media ◽  
Scanning Electron

Advancements in state of the art high density Head/Disk retrieval systems has increased the demand for sophisticated failure analysis methods. From 1968 to 1974 the emphasis was on the number of tracks per inch. (TPI) ranging from 100 to 400 as summarized in Table 1. This emphasis shifted with the increase in densities to include the number of bits per inch (BPI). A bit is formed by magnetizing the Fe203 particles of the media in one direction and allowing magnetic heads to recognize specific data patterns. From 1977 to 1986 the tracks per inch increased from 470 to 1400 corresponding to an increase from 6300 to 10,800 bits per inch respectively. Due to the reduction in the bit and track sizes, build and operating environments of systems have become critical factors in media reliability.Using the Ferrofluid pattern developing technique, the scanning electron microscope can be a valuable diagnostic tool in the examination of failure sites on disks.

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