High-Density Through-Wafer Electrical Interconnects in Pyrex Substrate Integrated With Micromirror Array

2003 ◽  
Author(s):  
C. C. Wang ◽  
T. D. Kudrle ◽  
M. Bancu ◽  
J. Hsiao ◽  
C. H. Mastrangelo
Keyword(s):  
Flip Chip ◽  
High Density ◽  
Anodic Bonding ◽  
Thermal Coefficient ◽  
Electrical Interconnects ◽  
Via Holes ◽  
Multiple Levels ◽  
Micromirror Array

A method for the construction of high density (2.4 mm−2) vertical leads through a pyrex substrate is presented. The pyrex substrate behaves as a TCE (Thermal Coefficient of Expansion) matched interposer that permits anodic bonding of silicon micromirrors on one side and flip-chip bumping of multiplexing electronic chips on its opposite side. Electrical leads consist of 250±25 μm-diameter holes formed by AJM machining and coated with evaporated Au yielding via resistances of 0.5–0.7 Ω. The via holes are sealed with a new spin-cast polyimide tenting process that enables the subsequent patterning of multiple levels of metal using conventional lithographic techniques.

scholarly journals Fabrication and Packaging of CMUT Using Low Temperature Co-Fired Ceramic

Micromachines ◽  
2018 ◽  
Vol 9 (11) ◽  
pp. 553 ◽  
Author(s):  
Fikret Yildiz ◽  
Tadao Matsunaga ◽  
Yoichi Haga
Keyword(s):  
Low Temperature ◽  
Integrated Circuit ◽  
Flip Chip ◽  
Ultrasonic Transducer ◽  
Silicon On Insulator ◽  
Anodic Bonding ◽  
Lateral Side ◽  
Membrane Thickness ◽  
Bonding Performance ◽  
Complex Admittance

This paper presents fabrication and packaging of a capacitive micromachined ultrasonic transducer (CMUT) using anodically bondable low temperature co-fired ceramic (LTCC). Anodic bonding of LTCC with Au vias-silicon on insulator (SOI) has been used to fabricate CMUTs with different membrane radii, 24 µm, 25 µm, 36 µm, 40 µm and 60 µm. Bottom electrodes were directly patterned on remained vias after wet etching of LTCC vias. CMUT cavities and Au bumps were micromachined on the Si part of the SOI wafer. This high conductive Si was also used as top electrode. Electrical connections between the top and bottom of the CMUT were achieved by Au-Au bonding of wet etched LTCC vias and bumps during anodic bonding. Three key parameters, infrared images, complex admittance plots, and static membrane displacement, were used to evaluate bonding success. CMUTs with a membrane thickness of 2.6 µm were fabricated for experimental analyses. A novel CMUT-IC packaging process has been described following the fabrication process. This process enables indirect packaging of the CMUT and integrated circuit (IC) using a lateral side via of LTCC. Lateral side vias were obtained by micromachining of fabricated CMUTs and used to drive CMUTs elements. Connection electrodes are patterned on LTCC side via and a catheter was assembled at the backside of the CMUT. The IC was mounted on the bonding pad on the catheter by a flip-chip bonding process. Bonding performance was evaluated by measurement of bond resistance between pads on the IC and catheter. This study demonstrates that the LTCC and LTCC side vias scheme can be a potential approach for high density CMUT array fabrication and indirect integration of CMUT-IC for miniature size packaging, which eliminates problems related with direct integration.

Combined Manufacture Methods for High Density LTCC Substrates: Thick Film Screen Printing, Ink Jet, Postfiring Thin Film Processes, and Laser-Drilled Fine Vias

2009 ◽  
Vol 6 (1) ◽  
pp. 6-12 ◽  
Author(s):  
Arne Albertsen ◽  
Koji Koiwai ◽  
Kyoji Kobayashi ◽  
Tomonori Oguchi ◽  
Katsumi Aruga
Keyword(s):  
Thin Film ◽  
Thick Film ◽  
Screen Printing ◽  
Flip Chip ◽  
High Density ◽  
Uv Laser ◽  
Fine Pitch ◽  
Ink Jet ◽  
Printing Ink ◽  
Base Substrate

This paper highlights the possible combination of technologies such as thick film screen printing, ink jet, and post-firing thin film processes in conjunction with laser-drilled fine vias to produce high-density, miniaturized LTCC substrates. To obtain the silver pattern on the inner layers, both conventional thick film printing and ink jet printing (using nano silver particle dispersed ink) were applied on the ceramic green sheets. The ink jet process made it possible to metallize fine lines with line/space = 30/30 μm. For interlayer connections, fine vias of 30 μm in diameter formed by UV laser were used. Then these sheets were stacked on top of each other and fired to obtain a base substrate. On this base substrate, fine copper patterns for flip chip mounting were formed by a thin film process. The surface finish consisted of a nickel passivation and a gold layer deposited by electroless plating. The combination of the three patterning processes for conducting traces and UV laser drilling of fine vias make it appear possible to realize fine pitch LTCC, for example, for flip chip device mounting.

Die to Die and Die To Wafer Bonding Solution for High Density, Fine Pitch Micro-Bumped Die

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 002251-002284 ◽  
Author(s):  
Gilbert Lecarpentier ◽  
Joeri De Vos
Keyword(s):  
Wafer Bonding ◽  
Flip Chip ◽  
High Accuracy ◽  
High Density ◽  
Size Reduction ◽  
Direct Impact ◽  
3 Dimensional ◽  
Fine Pitch ◽  
Placement Accuracy ◽  
Die Bonding

Higher density interconnection using 3-Dimensional technology implies a pitch reduction and the use of micro-bumps. The micro-bump size reduction has a direct impact on the placement accuracy needed on the die placement and flip chip bonding equipment. The paper presents a Die-to-Die and Die-to-Wafer, high accuracy, die bonding solution illustrated by the flip chip assembly of a large 2x2cm die consisting of 1 million 10 μm micro-bumps at 20 μm pitch

Precise Chip Joint Method with Sub-micron Au Particle for High-density SiC Power Module Operating at High Temperature

2013 ◽  
Vol 2013 (HITEN) ◽  
pp. 000254-000259 ◽  
Author(s):  
Fumiki Kato ◽  
Fengqun Lang ◽  
Simanjorang Rejeki ◽  
Hiroshi Nakagawa ◽  
Hiroshi Yamaguchi ◽  
...  
Keyword(s):  
Shear Strength ◽  
High Temperature ◽  
Flip Chip ◽  
Stress Test ◽  
High Density ◽  
Cathode Side ◽  
Module Structure ◽  
Power Devices ◽  
Power Module ◽  
Joint Method

In this work, a novel precise chip joint method using sub-micron Au particle for high-density silicon carbide (SiC) power module operating at high temperature is proposed. A module structure of SiC power devices are sandwiched between two silicon nitride-active metal brazed copper (SiN-AMC) circuit boards. To make a precise position and height control of the chip bonding, the top side (gate/source or anode pad side) of SiC power devices are flip-chip bonded to circuit electrodes using sub-micron Au particle with low temperature (250°C) and pressure-less sintering. The accuracy of the bonding position of chips was less than 10 μm and the accuracy of the height after bonding chips was less than 15 μm. Mechanical shear fatigue tests for flip-chip bonded SiC Schottky barrier diode (SBD) were carried out. As a result, initial shear strength of the joint was 36 MPa. The shear strength of 43 MPa is obtained after storage life test (500 hours at 250°C), and also 35 MPa is obtained even after thermal cycle stress test (1000 cycles between −40°C and 250°C). The flip-chip bonding of SiC-JFET is successfully realizedon the substrate without short or open failure electrically. Finally we joint the backside of the SiC-JFET (drain side) and the SiC-SBD (cathode side) to each circuit electrodes at once by means of reflow process with Au-12%Ge solder. The structured sandwich SiC power module was also successfully formed.

Comparison of different flex materials in high density flip chip on flex applications

2003 ◽  
Vol 43 (3) ◽  
pp. 445-451 ◽  
Author(s):  
Petteri Palm ◽  
Jarmo Määttänen ◽  
Yannick De Maquillé ◽  
Alain Picault ◽  
Jan Vanfleteren ◽  
...  
Keyword(s):  
Flip Chip ◽  
High Density

Optimizing System-on-Film (SOF) Design Using Finite Element Analysis

2011 ◽  
Author(s):  
Vikram Venkatadri ◽  
Mark Downey ◽  
Xiaojie Xue ◽  
Dipak Sengupta ◽  
Daryl Santos ◽  
...  
Keyword(s):  
Finite Element Analysis ◽  
Finite Element ◽  
Flip Chip ◽  
Flexible Substrate ◽  
High Density ◽  
Design Solution ◽  
Design Parameters ◽  
Optimized Design ◽  
Element Analysis ◽  
Bonding Parameters

System-On-Film (SOF) module is a complex integration of a fine pitch high density die and surface mounted discrete devices on a polyimide (PI) film laminate. The die is connected to the film using a thermo-compression flip-chip bonding (TCB) process which is capable of providing a very high density interconnect at less than 50um pitch. Several design and bonding parameters have to be controlled in order to achieve a reliable bond between the Au bumps on the die and the Sn plated Cu traces on the PI film. In the current work, the TCB process is studied using Finite Element Analysis (FEA) to optimize the design parameters and assure proper process margins. The resultant forces acting on the bump-to-trace interfaces are quantified across the different potential geometrical combinations. Baseline simulations showed higher stresses on specific bump locations and stress gradients acting on the bumps along the different sides of the die. These observations were correlated to both the failures and near failures on the actual test vehicles. Further simulations were then utilized to optimize and navigate design tradeoffs at both the die and flexible substrate design levels for a more robust design solution. Construction analysis performed on parts built using optimized design parameters showed significant improvements and correlated well with the simulation results.

Polyimide Multi-Layer Substrate for High-Density Semiconductor Package

2005 ◽  
Author(s):  
Shoichi Takenaka ◽  
Shoji Ito ◽  
Ryoichi Kishihara ◽  
Masahiro Okamoto ◽  
Osamu Nakao
Keyword(s):  
Conventional Method ◽  
Polyimide Film ◽  
High Density ◽  
Electrical Connection ◽  
Via Holes

We have developed a polyimide multi-layer substrate for semiconductor package. Interstitial via holes filled with conductive paste make the electrical connection in any layers in the multi-layer substrate to realize high-density wiring. The substrate shows reliable resistance to moisture and heat. Use of polyimide film make the substrate considerable thin compared to the conventional method using glass-epoxy. The present multi-layer substrate can be applied to a promising interposer for high-density semiconductor such as multi-chip module and stacked chip.

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