Development of High Reliability Via on IVH (VONI) for High Density Interconnect Circuit Boards

2007 ◽  
Vol 4 (2) ◽  
pp. 78-85
Author(s):  
Jong-Won Park ◽  
Yun-Seok Hwang ◽  
Il-Kyoon Jeun ◽  
Da-Hee Joung ◽  
Myung-Gun Chong ◽  
...  

Via on interstitial via hole (VONI) technique is a complex set of technologies for blind and buried vias in traditional sequential lamination cycles with external layers, and micro via holes (MVH) for true high-density packaging. However, when VONI is repeatedly subjected to thermal stress, the interstitial via hole (IVH) in its structure often creates problems such as IVH barrel cracks, and layer-layer delamination. To solve VONI's reliability problems, such as IVH barrel crack and layer-layer delamination, the authors have investigated the relationship between the CTE difference and the effect of moisture. Through using different types of plugging inks, it was clearly indicated that delamination was related to the chemical properties of the plugging inks. For example delamination was dominated by the inks property of water adsorption, which induced vapor pressure when it undergoes thermal shock testing. The authors have solved the delamination problem by reducing the ratio of water adsorption in the plugging ink.

Author(s):  
Kenji Hirohata ◽  
Yousuke Hisakuni ◽  
Takahiro Omori ◽  
Tomoko Monda ◽  
Minoru Mukai

Continuing improvements in both capacity and miniaturization of electronic equipment such as solid state drives (SSDs) are spurring demand for high-density packaging of NAND-type flash memory mounted on SSD printed circuit boards. High-density packaging leads to increased fatigue failure risk of solder joints due to the decreased reliability margin for stress. We have developed a failure precursor detection technology based on fatigue failure probability estimation during use. This method estimates the cycles to fatigue failure of an actual circuit by detecting broken connections in a canary circuit (a dummy circuit of daisy-chained solder joints). The canary circuit is designed to fail earlier than the actual circuit under the same failure mode by using accelerated reliability testing and inelastic stress simulation. The statistical distribution of the strain range of solder joints can be provided by Monte Carlo simulations based on the finite element method and random load modeling. A feasibility study of the failure probability estimation method is conducted by applying the method to a printed circuit board on which a ball grid array (BGA) package is mounted using BGA solder joints. The proposed method is found to be useful for prognostic health monitoring of solder joint’s fatigue failure.


Author(s):  
Nobuki Ueta ◽  
Shunsuke Sato ◽  
Masakazu Sato ◽  
Yoshio Nakao ◽  
Joshua Magnuson ◽  
...  

Abstract Miniaturization of electronics modules is always required for various medical applications including wearable technology, such as hearing aids, and implantable devices. Many types of high-density packaging technologies, such as package-on-package, bare-die stack, flex folded package and Through Si Via (TSV) technologies, have been proposed and used to fulfill the request. Among them, embedded die technology is one of the promising technologies to realize miniaturization and high-density packaging. We have developed WABE™ (wafer and board level device embedded) technology for embedding dies into multilayer flexible printed circuit (FPC) boards. The WABE package is comprised of thin dies (85 μm thickness), multi-layer polyimide, adhesive films and conductive paste. The dies are sandwiched by polyimide films with Cu circuits (FPCs). The conductive paste provides electrical connections between the layers as well as the layer and embedded die. First, each FPC layer is fabricated individually, and via holes are filled with conductive paste, and the dies are mounted on certain layers. Then, all layers undergo a one-step co-lamination process, and they are pressed to cure the adhesive material and conductive paste at the same time. This WABE technology has enabled multiple dies to be embedded by the one-step lamination process. Even if multiple dies are embedded, the footprint of a package can be reduced drastically by embedding multiple dies vertically in stacks. This paper describes the details of the results of fabricating a test vehicle with six embedded dies (three-dies in two stacks side-by-side). The fabricated test vehicle had 14 copper layers with less than 0.9 mm thickness. This paper also reports the results of various reliability testing on the package. These results were obtained by electrical measurements of daisy chain patterns formed between some of the layers. The fabricated test vehicle showed high reliability based on the results of a moisture and heat test and heat-shock test. These results show that the WABE technology to embed multiple dies vertically in polyimide film is one of the most promising packaging technologies to significantly miniaturize electronic circuits such as medical electronics.


2018 ◽  
Vol 21 (3) ◽  
pp. 190-192
Author(s):  
Yasuhiro Morikawa ◽  
Muneyuki Sato ◽  
Takahide Murayama ◽  
Toshiyuki Sakuishi ◽  
Tetsushi Fujinaga

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