Quantum-Well Si/SiC Self-Cooling for Thermal Management of High Heat Flux GaN HEMT Semiconductor Devices

Author(s):  
Peng Wang ◽  
Michael Manno ◽  
Avram Bar-Cohen

Wide bandgap semiconductor technology is expected to have a dramatic impact on radar and communications systems. To take full advantage of the power capabilities and small device sizes of wide bandgap semiconductors, new and novel thermal management solutions, especially for high power density, monolithic microwave integrated circuits (MMICs) are in high demand. In this paper, a quantum-well Si/SiC self-cooling concept for hot spot thermal management at the multi-fingered GaN high electron mobility transistor (HEMTs) in the GaN-on-SiC package is proposed and investigated using a three dimensional (3-D) thermal-electric coupling simulation. The impact of electric current, cooler size, Si/SiC substrate thickness, Si/SiC thermal conductivity, and interfacial parasitic effect on the hot spot cooling is examined and discussed. The preliminary modeling results strongly suggest that self-cooling phenomenon inherent in the quantum-well Si/SiC substrate can be used to remove local high heat flux hot spot on the semiconductor devices.

Author(s):  
Avram Bar-Cohen ◽  
Peng Wang

The rapid emergence of nanoelectronics, with the consequent rise in transistor density and switching speed, has led to a steep increase in microprocessor chip heat flux and growing concern over the emergence of on-chip “hot spots”. The application of on-chip high heat flux cooling techniques is today a primary driver for innovation in the electronics industry. In this paper, the physical phenomena underpinning the most promising on-chip thermal management approaches for hot spot remediation, along with basic modeling equations and typical results are described. Attention is devoted to thermoelectric microcoolers — using mini-contcat enhancement and in-plane thermoelectric currents, orthotropic TIM’s/heat spreaders, and phase-change microgap coolers.


2012 ◽  
Vol 134 (5) ◽  
Author(s):  
Avram Bar-Cohen ◽  
Peng Wang

The rapid emergence of nanoelectronics, with the consequent rise in transistor density and switching speed, has led to a steep increase in microprocessor chip heat flux and growing concern over the emergence of on-chip hot spots. The application of on-chip high flux cooling techniques is today a primary driver for innovation in the electronics industry. In this paper, the physical phenomena underpinning the most promising on-chip thermal management approaches for hot spot remediation, along with basic modeling equations and typical results are described. Attention is devoted to thermoelectric micro-coolers and two-phase microgap coolers. The advantages and disadvantages of these on-chip cooling solutions for high heat flux hot spots are evaluated and compared.


Author(s):  
Gary L. Solbrekken

Localized areas of high heat flux on microprocessors are currently being identified as a dominant challenge for the thermal management community. Heat flux values up to 1 kW/cm2 prevailing over a fraction of the overall CPU surface area create local hot spots that need to be cooled. However, thermal solutions designed for the maximum heat flux overcool the rest of the CPU, wasting resources and creating large on-die temperature gradients. Wasting resources obviously has a negative economic and thermodynamic impact. However, it has been argued that large on-die temperature gradients reduce chip reliability and increase the difficulty in laying out the electric circuits. The current study proposes a strategy to reduce local hot spots by enhancing heat spreading through the use of the Peltier effect. The Peltier effect is most commonly associated with the operation of thermoelectric modules. In thermoelectric modules, heat is transported across the module by electrons. Ideally, the material used for the thermoelectric module would have a very low thermal conductivity to reduce the amount of back heat conduction through the thermoelectric elements, and the electric resistivity would be very low to minimize the Joule heating. Using today’s best commercially available thermoelectric materials, the thermal conductivity, electric resistivity, and Seebeck coefficient are such that the COP for the thermoelectric module is on the order of 1. This implies that in order to cool a processor dissipating 100W, an additional 100W of electric power must be supplied to the thermoelectric module. A total of 200W must then be rejected by the heat sink and any building HVAC system. A more pragmatic approach is to use the Peltier effect to not cool the entire CPU, but rather only the high heat flux region. This is accomplished by placing the thermoelectric elements laterally on the backside of the CPU. The cooling junction is placed in the proximity of the high flux region, while the heating junction is placed in contact with the CPU in low heat flux area that can tolerate the additional heat, effectively creating an active heat spreader. The Peltier enhanced heat spreading proposed here is shown to provide a reduction in the temperature of a localized hot spot relative to passive heat spreading. The amount of reduction in temperature depends on the thickness of the material as well as the thermal conductivity, but values up to 50% are illustrated.


2013 ◽  
Vol 455 ◽  
pp. 466-469
Author(s):  
Yun Chuan Wu ◽  
Shang Long Xu ◽  
Chao Wang

With the increase of performance demands, the nonuniformity of on-chip power dissipation becomes greater, causing localized high heat flux hot spots that can degrade the processor performance and reliability. In this paper, a three-dimensional model of the copper microchannel heat sink, with hot spot heating and background heating on the back, was developed and used for numerical simulation to predict the hot spot cooling performance. The hot spot is cooled by localized cross channels. The pressure drop, thermal resistance and effects of hot spot heat flux and fluid flow velocity on the cooling of on-chip hot spots, are investigated in detail.


2015 ◽  
Vol 137 (3) ◽  
Author(s):  
Abas Abdoli ◽  
George S. Dulikravich ◽  
Genesis Vasquez ◽  
Siavash Rastkar

Two-layer single phase flow microchannels were studied for cooling of electronic chips with a hot spot. A chip with 2.45 × 2.45 mm footprint and a hot spot of 0.5 × 0.5 mm in its center was studied in this research. Two different cases were simulated in which heat fluxes of 1500 W cm−2 and 2000 W cm−2 were applied at the hot spot. Heat flux of 1000 W cm−2 was applied on the rest of the chip. Each microchannel layer had 20 channels with an aspect ratio of 4:1. Direction of the second microchannel layer was rotated 90 deg with respect to the first layer. Fully three-dimensional (3D) conjugate heat transfer analysis was performed to study the heat removal capacity of the proposed two-layer microchannel cooling design for high heat flux chips. In the next step, a linear stress analysis was performed to investigate the effects of thermal stresses applied to the microchannel cooling design due to variations of temperature field. Results showed that two-layer microchannel configuration was capable of removing heat from high heat flux chips with a hot spot.


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