Fabrication of bipolar transistors by maskless ion implantation

1986 ◽  
Vol 4 (1) ◽  
pp. 290 ◽  
Author(s):  
Robert H. Reuss
Keyword(s):  
Ion Implantation ◽  
Bipolar Transistors

Characteristics of Bipolar Transistors with Various Depths of n+Buried Layers Formed by High-Energy Ion Implantation

1992 ◽  
Vol 31 (Part 1, No. 2A) ◽  
pp. 156-160 ◽  
Author(s):  
Akihiro Tamba ◽  
Yutaka Kobayashi ◽  
Tadashi Suzuki ◽  
Nobuyoshi Natsuaki
Keyword(s):  
Ion Implantation ◽  
High Energy ◽  
Bipolar Transistors ◽  
Buried Layers

Electrical Measurement of the Bandgap of N+ and P+ SiGe Formed by Ge Ion Implantation

1997 ◽  
Vol 500 ◽  
Author(s):  
Akira Nishiyama ◽  
Osamu Arisumi ◽  
Makoto Yoshimi
Keyword(s):  
Ion Implantation ◽  
Theoretical Calculation ◽  
Temperature Dependence ◽  
Electrical Measurement ◽  
Bipolar Transistors ◽  
Floating Body ◽  
High Dose ◽  
Base Current ◽  
Source Regions ◽  
Heavily Doped

ABSTRACTN+ and p+ SiGe layers were formed in the source regions of SOI MOSFETs in order to suppress the floating-body effects by means of high-dose Ge implantation. The bandgaps of the layers were evaluated by measuring the temperature dependence of the base current of the source/channel/drain lateral bipolar transistors. It has been found that the reductions of the bandgaps due to the SiGe formation by the Ge implantation were relatively small, compared to those obtained by the theoretical calculation for heavily doped SiGe. It was also found that the bandgap reduction was larger for n+ layers than that for p+ layers.

Effect of Current-Spreading Layer Formed by Ion Implantation on the Electrical Properties of High-Voltage 4H-SiC p-Channel IGBTs

2014 ◽  
Vol 778-780 ◽  
pp. 1038-1041 ◽  
Author(s):  
Tadayoshi Deguchi ◽  
Shuji Katakami ◽  
Hiroyuki Fujisawa ◽  
Kensuke Takenaka ◽  
Hitoshi Ishimori ◽  
...  
Keyword(s):  
Ion Implantation ◽  
High Voltage ◽  
Room Temperature ◽  
Voltage Drop ◽  
Temperature Stability ◽  
Bipolar Transistors ◽  
Forward Voltage ◽  
Current Spreading ◽  
Blocking Voltage ◽  
Forward Voltage Drop

High-voltage SiC p-channel insulated-gate bipolar transistors (p-IGBT) utilizing current-spreading layer (CSL) formed by ion implantation are fabricated and their properties characterized. A high blocking voltage of 15 kV is achieved at room temperature by optimizing the JFET length. An ampere-class p-IGBT exhibited a low forward voltage drop of 8.5 V at 100 A/cm2 and a low differential specific on-resistance of 33 mΩ cm2 at 250 °C, while these values were high at room temperature. For further reduction of the forward voltage drop in the on-state and temperature stability, the temperature dependence of the JFET effect and carrier lifetime in p-IGBTs are investigated. Optimization of the JFET length using an epitaxial CSL, instead of applying ion implantation and lifetime enhancement, could lead to a further reduction of the forward voltage drop.

Use of MeV O+ion implantation for isolation of GaAs/AlGaAs heterojunction bipolar transistors

1992 ◽  
Vol 71 (10) ◽  
pp. 4949-4954 ◽  
Author(s):  
S. J. Pearton ◽  
F. Ren ◽  
J. R. Lothian ◽  
T. R. Fullowan ◽  
A. Katz ◽  
...  
Keyword(s):  
Ion Implantation ◽  
Heterojunction Bipolar Transistors ◽  
Bipolar Transistors
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