Ratcheting quasi-ballistic electrons in silicon geometric diodes at room temperature

Science ◽  
2020 ◽  
Vol 368 (6487) ◽  
pp. 177-180 ◽  
Author(s):  
James P. Custer ◽  
Jeremy D. Low ◽  
David J. Hill ◽  
Taylor S. Teitsworth ◽  
Joseph D. Christesen ◽  
...  
Keyword(s):  
High Speed ◽  
Room Temperature ◽  
Specular Reflection ◽  
Three Dimensional ◽  
Nanowire Diameter ◽  
Semiconductor Nanowire ◽  
Long Wavelength ◽  
Underlying Principle ◽  
Nanowire Surface ◽  
High Speed Data

Ratcheting effects play an important role in systems ranging from mechanical socket wrenches to biological motor proteins. The underlying principle is to convert a fluctuating, unbiased force into unidirectional motion. Here, we report the ratcheting of electrons at room temperature using a semiconductor nanowire with precisely engineered asymmetry. Modulation of the nanowire diameter creates a cylindrical sawtooth geometry with broken inversion symmetry on a nanometer-length scale. In a two-terminal device, this structure responded as a three-dimensional geometric diode that funnels electrons preferentially in one direction through specular reflection of quasi-ballistic electrons at the nanowire surface. The ratcheting effect causes charge rectification at frequencies exceeding 40 gigahertz, demonstrating the potential for applications such as high-speed data processing and long-wavelength energy harvesting.

Through-Silicon Photonic Via and Unidirectional Coupler for High-Speed Data Transmission in Optoelectronic Three-Dimensional LSI

2012 ◽  
Vol 33 (2) ◽  
pp. 221-223 ◽  
Author(s):  
Akihiro Noriki ◽  
Kangwook Lee ◽  
Jicheol Bea ◽  
Takafumi Fukushima ◽  
Tetsu Tanaka ◽  
...  
Keyword(s):  
Data Transmission ◽  
High Speed ◽  
Three Dimensional ◽  
Silicon Photonic ◽  
High Speed Data ◽  
Speed Data Transmission

Observations of Precipitates In 95PB-5SN Solder

1985 ◽  
Vol 43 ◽  
pp. 342-343 ◽  
Author(s):  
Darrel Frear ◽  
J. W. Morris
Keyword(s):  
Data Processing ◽  
Equilibrium State ◽  
Integrated Circuit ◽  
Electronic Packaging ◽  
High Speed ◽  
Room Temperature ◽  
Limiting Factor ◽  
Fundamental Study ◽  
High Speed Data

The electronic packaging of integrated circuit chips has been cited as the limiting factor in the performance and reliability of high speed data processing units. A very important part of the package is in the first level where solder bonds the IC chip to a ceramic carrier. The most commonly used first level solder is 95Pb-5Sn. The importance of this solder connection instigated the following fundamental study of the microstructure of 95Pb-5Sn and its precipitates.The alloy was melted in vacuum at 400°C using 99.9% pure Pb and Sn. The ingot was allowed to cool and age for a few days at room temperature. TEM 3mm foils were cut and mechanically thinned down to 4 mil thickness. After aging at room temperature the solder is considered to be in its equilibrium state, no further changes in microstructure are observed.

TEM study of phosphorus-implanted pseudomorphic Si0.88Ge0.12 on Si(100)

1995 ◽  
Vol 53 ◽  
pp. 468-469
Author(s):  
N. David Theodore ◽  
Donald Y.C Lie ◽  
J. H. Song ◽  
Peter Crozier
Keyword(s):  
Integrated Circuits ◽  
Heterojunction Bipolar Transistors ◽  
Integrated Circuit ◽  
High Speed ◽  
Room Temperature ◽  
Strain Relaxation ◽  
Bipolar Transistors ◽  
Sige Hbt ◽  
Integrated Circuit Manufacturing ◽  
Microstructural Behavior

SiGe is being extensively investigated for use in heterojunction bipolar-transistors (HBT) and high-speed integrated circuits. The material offers adjustable bandgaps, improved carrier mobilities over Si homostructures, and compatibility with Si-based integrated-circuit manufacturing. SiGe HBT performance can be improved by increasing the base-doping or by widening the base link-region by ion implantation. A problem that arises however is that implantation can enhance strain-relaxation of SiGe/Si.Furthermore, once misfit or threading dislocations result, the defects can give rise to recombination-generation in depletion regions of semiconductor devices. It is of relevance therefore to study the damage and anneal behavior of implanted SiGe layers. The present study investigates the microstructural behavior of phosphorus implanted pseudomorphic metastable Si0.88Ge0.12 films on silicon, exposed to various anneals.Metastable pseudomorphic Si0.88Ge0.12 films were grown ~265 nm thick on a silicon wafer by molecular-beam epitaxy. Pieces of this wafer were then implanted at room temperature with 100 keV phosphorus ions to a dose of 1.5×1015 cm-2.

High-speed brightfield 3-D imaging and 3-D image analysis of thick and overlapped cell clusters in cytological preparations

1994 ◽  
Vol 52 ◽  
pp. 218-219
Author(s):  
Robert W. Mackin
Keyword(s):  
Image Analysis ◽  
High Speed ◽  
Three Dimensional ◽  
Image Data ◽  
Ccd Camera ◽  
Objective Lens ◽  
Array Processor ◽  
Vaginal Smears ◽  
Low Contrast ◽  
Computer Controlled

This paper presents two advances towards the automated three-dimensional (3-D) analysis of thick and heavily-overlapped regions in cytological preparations such as cervical/vaginal smears. First, a high speed 3-D brightfield microscope has been developed, allowing the acquisition of image data at speeds approaching 30 optical slices per second. Second, algorithms have been developed to detect and segment nuclei in spite of the extremely high image variability and low contrast typical of such regions. The analysis of such regions is inherently a 3-D problem that cannot be solved reliably with conventional 2-D imaging and image analysis methods.High-Speed 3-D imaging of the specimen is accomplished by moving the specimen axially relative to the objective lens of a standard microscope (Zeiss) at a speed of 30 steps per second, where the stepsize is adjustable from 0.2 - 5μm. The specimen is mounted on a computer-controlled, piezoelectric microstage (Burleigh PZS-100, 68/μm displacement). At each step, an optical slice is acquired using a CCD camera (SONY XC-11/71 IP, Dalsa CA-D1-0256, and CA-D2-0512 have been used) connected to a 4-node array processor system based on the Intel i860 chip.

Valence electron energy loss spectroscopy in reflection geometry

1989 ◽  
Vol 47 ◽  
pp. 378-379
Author(s):  
J. Liu ◽  
J. M. Cowley
Keyword(s):  
Energy Loss ◽  
Valence Electron ◽  
Interband Transition ◽  
Specular Reflection ◽  
Three Dimensional ◽  
Electron Excitation ◽  
Transmission Electron ◽  
Yield Information ◽  
Valence Bands ◽  
Excitation Processes

The low energy loss region of a EELS spectrum carries information about the valence electron excitation processes (e.g., collective excitations for free electron like materials and interband transitions for insulators). The relative intensities and the positions of the interband transition energy loss peaks observed in EELS spectra are determined by the joint density of states (DOS) of the initial and final states of the excitation processes. Thus it is expected that EELS in reflection mode could yield information about the perturbation of the DOS of the conduction and valence bands of the bulk crystals caused by the termination of the three dimensional periodicity at the crystal surfaces. The experiments were performed in a Philipps 400T transmission electron microscope operated at 120 kV. The reflection EELS spectra were obtained by a Gatan 607 EELS spectrometer together with a Tracor data acquisition system and the resolution of the spectrometer was about 0.8 eV. All the reflection spectra are obtained from the specular reflection spots satisfying surface resonance conditions.

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