Electrical characterization of fluorine-implanted gate oxide structures

In the ongoing quest for thinner and more reliable gate dielectrics for microelectronics, fluorination of gate oxide structures has emerged as a leading technique. In this work, the fluorine is implanted into the polysilicon gate before the poly etch. After the subsequent poly etch and anneal, the samples are not sent through the remainder of the process, but are subjected to electrical reliability stressing by two methods: constant-current Fowler–Nordheim tunnelling stress, and constant-voltage stress (J–t analysis). Two different fluorination cases (doses and implant energies) are studied, along with unimplanted controls. In the fluorinated cases, improvement vs. controls is found in device reliability indicators: mid-gap Dit, Qf, and ΔVth. J–t analysis corroborates the improvement, and the combination of techniques is found to offer a more, comprehensive view of complex variations in fluorinated oxide properties.