Quantum Dot Channel (QDC) Field Effect Transistors (FETs) Configured as Floating Gate Nonvolatile Memories (NVMs)

Author(s):  
Jun Kondo ◽  
Murali Lingalugari ◽  
Pial Mirdha ◽  
Pik-Yiu Chan ◽  
Evan Heller ◽  
...  
2001 ◽  
Vol 40 (Part 2, No. 7B) ◽  
pp. L721-L723 ◽  
Author(s):  
Atsushi Kohno ◽  
Hideki Murakami ◽  
Mitsuhisa Ikeda ◽  
Seiichi Miyazaki ◽  
Masataka Hirose

2015 ◽  
Vol 44 (9) ◽  
pp. 3188-3193 ◽  
Author(s):  
J. Kondo ◽  
M. Lingalugari ◽  
P.-Y. Chan ◽  
E. Heller ◽  
F. Jain

2017 ◽  
Vol 26 (03) ◽  
pp. 1740015
Author(s):  
Jun Kondo ◽  
Murali Lingalugari ◽  
Pial Mirdha ◽  
Pik-Yiu Chan ◽  
Evan Heller ◽  
...  

This paper presents quantum dot channel (QDC) Field Effect Transistors (FETs) which are configured as nonvolatile memories (NVMs) by incorporating cladded GeOx-Ge quantum dots in the floating gates as well as the transport channels. The current flow and the threshold characteristics were significantly improved when the gate dielectric was changed from silicon dioxide (SiO2) to hafnium aluminum oxide (HfAlO2), and the control dielectric was changed from silicon nitride (Si3N4) to hafnium aluminum oxide (HfAlO2). The device operations are explained by carrier transport in narrow energy mini-bands which are manifested in a quantum dot transport channel.


2013 ◽  
Vol 16 (9) ◽  
pp. 312-325 ◽  
Author(s):  
Frederik Hetsch ◽  
Ni Zhao ◽  
Stephen V. Kershaw ◽  
Andrey L. Rogach

2019 ◽  
Vol 28 (03n04) ◽  
pp. 1940025
Author(s):  
H. Salama ◽  
B. Saman ◽  
R. H. Gudlavalleti ◽  
P-Y. Chan ◽  
R. Mays ◽  
...  

This paper presents simulation of spatial wavefunction switched (SWS) field-effect transistors (FETs) comprising of two vertically stacked quantum dot channels. An analog behavior model (ABM) was used to compare the experimental I-V characteristics of a fabricated QD-SWS-FET. Each channel consists of two quantum dot layers and are connected to the dedicated drains D2 and D1, respectively. The fabricated SWS-FET has one source and one gate. The ABM simulation models SWS-FET comprising of two independent conventional BSIM FETs with their (W/L) ratios, capacitances and other device parameters. The agreement in simulation and experimental data will advance modeling of SWS based adders, logic gates and SRAMs.


ACS Nano ◽  
2020 ◽  
Vol 14 (5) ◽  
pp. 5754-5762 ◽  
Author(s):  
Maria El Abbassi ◽  
Mickael L. Perrin ◽  
Gabriela Borin Barin ◽  
Sara Sangtarash ◽  
Jan Overbeck ◽  
...  

2020 ◽  
Vol 12 (19) ◽  
pp. 21944-21951
Author(s):  
Dae-Kyu Kim ◽  
Dongsun Choi ◽  
Mihyeon Park ◽  
Kwang Seob Jeong ◽  
Jong-Ho Choi

Nano Letters ◽  
2013 ◽  
Vol 13 (8) ◽  
pp. 3463-3469 ◽  
Author(s):  
Tyler Otto ◽  
Chris Miller ◽  
Jason Tolentino ◽  
Yao Liu ◽  
Matt Law ◽  
...  

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