CHAOS-BASED MIXED SIGNAL IMPLEMENTATION OF SPIKING NEURONS

A new design of Spiking Neural Networks is proposed and fabricated using a 0.35 μm CMOS technology. The architecture is based on the use of both digital and analog circuitry. The digital circuitry is dedicated to the inter-neuron communication while the analog part implements the internal non-linear behavior associated to spiking neurons. The main advantages of the proposed system are the small area of integration with respect to digital solutions, its implementation using a standard CMOS process only and the reliability of the inter-neuron communication.

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SPIKING NEURAL NETWORKS

International Journal of Neural Systems ◽

10.1142/s0129065709002002 ◽

2009 ◽

Vol 19 (04) ◽

pp. 295-308 ◽

Cited By ~ 328

Author(s):

SAMANWOY GHOSH-DASTIDAR ◽

HOJJAT ADELI

Keyword(s):

Neural Networks ◽

Pattern Recognition ◽

Information Transfer ◽

Spiking Neurons ◽

Spiking Neural Networks ◽

Classification Problems ◽

Temporal Dimension ◽

Information Encoding ◽

Dynamic Representation ◽

Insight Into

Most current Artificial Neural Network (ANN) models are based on highly simplified brain dynamics. They have been used as powerful computational tools to solve complex pattern recognition, function estimation, and classification problems. ANNs have been evolving towards more powerful and more biologically realistic models. In the past decade, Spiking Neural Networks (SNNs) have been developed which comprise of spiking neurons. Information transfer in these neurons mimics the information transfer in biological neurons, i.e., via the precise timing of spikes or a sequence of spikes. To facilitate learning in such networks, new learning algorithms based on varying degrees of biological plausibility have also been developed recently. Addition of the temporal dimension for information encoding in SNNs yields new insight into the dynamics of the human brain and could result in compact representations of large neural networks. As such, SNNs have great potential for solving complicated time-dependent pattern recognition problems because of their inherent dynamic representation. This article presents a state-of-the-art review of the development of spiking neurons and SNNs, and provides insight into their evolution as the third generation neural networks.

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Quantized state simulation of spiking neural networks

SIMULATION ◽

10.1177/0037549711399935 ◽

2011 ◽

Vol 88 (3) ◽

pp. 299-313 ◽

Cited By ~ 12

Author(s):

Guillermo L Grinblat ◽

Hernán Ahumada ◽

Ernesto Kofman

Keyword(s):

Neural Networks ◽

Discrete Time ◽

Discrete Event ◽

State System ◽

Spiking Neurons ◽

Spiking Neural Networks ◽

Computational Costs ◽

Simulation Results ◽

Neuroscience Community

In this work, we explore the usage of quantized state system (QSS) methods in the simulation of networks of spiking neurons. We compare the simulation results obtained by these discrete-event algorithms with the results of the discrete time methods in use by the neuroscience community. We found that the computational costs of the QSS methods grow almost linearly with the size of the network, while they grows at least quadratically in the discrete time algorithms. We show that this advantage is mainly due to the fact that QSS methods only perform calculations in the components of the system that experience activity.

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A CMOS Low-Voltage Super Follower Using Quasi-Floating Gate Techniques

Journal of Circuits System and Computers ◽

10.1142/s0218126618501116 ◽

2018 ◽

Vol 27 (07) ◽

pp. 1850111 ◽

Cited By ~ 3

Author(s):

J. J. Ocampo-Hidalgo ◽

J. Alducín-Castillo ◽

I. Vázquez-Álvarez ◽

L. N. Oliva-Moreno ◽

J. E. Molinar-Solís

Keyword(s):

High Resistance ◽

Small Area ◽

Low Voltage ◽

Cmos Technology ◽

Floating Gate ◽

Process Models ◽

Cmos Process ◽

Gain Bandwidth ◽

Measurement Results ◽

Improved Performance

A quasi-floating gate (QFG) “super-follower” is presented. The high resistance used by the QFG transistor is constructed by two diodes connected back-to-back, leading to a simple-, temperature-stable- and small-area solution. Expressions for the behavior of the follower are introduced and verified by circuit simulations in LTSPICE using 0.5[Formula: see text][Formula: see text]m CMOS process models, which show an improved performance of the proposed circuit with respect to the original super-follower. To prove the principle, a test cell was fabricated in the same 0.5[Formula: see text][Formula: see text]m CMOS technology and characterized. Measurement results show a gain-bandwidth product of 10[Formula: see text]MHz and power consumption of 120[Formula: see text][Formula: see text]W with a 1.5[Formula: see text]V single supply.

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Neuroscience-Inspired Parameter Selection of Spiking Neuron Using Hodgkin Huxley Model

International Journal of Software Science and Computational Intelligence ◽

10.4018/ijssci.2021040105 ◽

2021 ◽

Vol 13 (2) ◽

pp. 89-106

Author(s):

Ruchi Holker ◽

Seba Susan

Keyword(s):

Neural Networks ◽

Spiking Neurons ◽

Spiking Neural Networks ◽

Model Parameters ◽

Spiking Neuron ◽

Artificial Brain ◽

Class 1 ◽

Optimal Values ◽

Neuron Simulator ◽

Selection Of

Spiking neural networks (SNN) are currently being researched to design an artificial brain to teach it how to think, perform, and learn like a human brain. This paper focuses on exploring optimal values of parameters of biological spiking neurons for the Hodgkin Huxley (HH) model. The HH model exhibits maximum number of neurocomputational properties as compared to other spiking models, as per previous research. This paper investigates the HH model parameters of Class 1, Class 2, phasic spiking, and integrator neurocomputational properties. For the simulation of spiking neurons, the NEURON simulator is used since it is easy to understand and code.

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An ultra-compact leaky integrate-and-fire neuron with long and tunable time constant utilizing pseudo resistors for spiking neural networks

Japanese Journal of Applied Physics ◽

10.35848/1347-4065/ac43e4 ◽

2021 ◽

Author(s):

Xiangyu Chen ◽

Takeaki Yajima ◽

Isao H. Inoue ◽

Tetsuya Iizuka

Keyword(s):

Neural Networks ◽

Time Constant ◽

Biological Networks ◽

Large Scale ◽

Cmos Technology ◽

Spiking Neural Networks ◽

Neuron Circuit ◽

Area Efficiency ◽

Integrate And Fire ◽

Lif Neuron

Abstract Spiking neural networks (SNNs) inspired by biological neurons enable a more realistic mimicry of the human brain. To realize SNNs similar to large-scale biological networks, neuron circuits with high area efficiency are essential. In this paper, we propose a compact leaky integrate-and-fire (LIF) neuron circuit with a long and tunable time constant, which consists of a capacitor and two pseudo resistors (PRs). The prototype chip was fabricated with TSMC 65 nm CMOS technology, and it occupies a die area of 1392 m2. The fabricated LIF neuron has a power consumption of 6 W and a leak time constant of up to 1.2 ms (the resistance of PR is up to 600 MΩ). In addition, the time constants are tunable by changing the bias voltage of PRs. Overall, this proposed neuron circuit facilitates the very-large-scale integration (VLSI) of adaptive SNNs, which is crucial for the implementation of bio-scale brain-inspired computing.

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A Reconfigurable and Biologically Inspired Paradigm for Computation Using Network-On-Chip and Spiking Neural Networks

International Journal of Reconfigurable Computing ◽

10.1155/2009/908740 ◽

2009 ◽

Vol 2009 ◽

pp. 1-13 ◽

Cited By ~ 37

Author(s):

Jim Harkin ◽

Fearghal Morgan ◽

Liam McDaid ◽

Steve Hall ◽

Brian McGinley ◽

...

Keyword(s):

Neural Networks ◽

Network Architecture ◽

Fault Tolerant ◽

Network On Chip ◽

Spiking Neurons ◽

Spiking Neural Networks ◽

Neural Network Architecture ◽

Biologically Inspired ◽

Field Programmable ◽

On Chip

FPGA devices have emerged as a popular platform for the rapid prototyping of biological Spiking Neural Networks (SNNs) applications, offering the key requirement of reconfigurability. However, FPGAs do not efficiently realise the biologically plausible neuron and synaptic models of SNNs, and current FPGA routing structures cannot accommodate the high levels of interneuron connectivity inherent in complex SNNs. This paper highlights and discusses the current challenges of implementing scalable SNNs on reconfigurable FPGAs. The paper proposes a novel field programmable neural network architecture (EMBRACE), incorporating low-power analogue spiking neurons, interconnected using a Network-on-Chip architecture. Results on the evaluation of the EMBRACE architecture using the XOR benchmark problem are presented, and the performance of the architecture is discussed. The paper also discusses the adaptability of the EMBRACE architecture in supporting fault tolerant computing.

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Hybrid memristor-CMOS neurons for in situ learning in fully hardware memristive spiking neural networks

10.21203/rs.3.rs-43977/v1 ◽

2020 ◽

Author(s):

Xumeng Zhang ◽

Jian Lu ◽

Rui Wang ◽

Jinsong Wei ◽

Tuo Shi ◽

...

Keyword(s):

Neural Network ◽

Neural Networks ◽

Hebbian Learning ◽

Spiking Neurons ◽

Spiking Neural Networks ◽

Spiking Neural Network ◽

Neuromorphic Computing ◽

Efficient Data ◽

Neuron Function

Abstract Spiking neural network, consisting of spiking neurons and plastic synapses, is a promising but relatively underdeveloped neural network for neuromorphic computing. Inspired by the human brain, it provides a unique solution for highly efficient data processing. Recently, memristor-based neurons and synapses are becoming intriguing candidates to build spiking neural networks in hardware, owing to the close resemblance between their device dynamics and the biological counterparts. However, the functionalities of memristor-based neurons are currently very limited, and a hardware demonstration of fully memristor-based spiking neural networks supporting in situ learning is very challenging. Here, a hybrid spiking neuron by combining the memristor with simple digital circuits is designed and implemented in hardware to enhance the neuron functions. The hybrid neuron with memristive dynamics not only realizes the basic leaky integrate-and-fire neuron function but also enables the in situ tuning of the connected synaptic weights. Finally, a fully hardware spiking neural network with the hybrid neurons and memristive synapses is experimentally demonstrated for the first time, with which in situ Hebbian learning is achieved. This work opens up a way towards the implementation of spiking neurons, supporting in situ learning for future neuromorphic computing systems.

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