A CMOS Low-Voltage Super Follower Using Quasi-Floating Gate Techniques

2018 ◽  
Vol 27 (07) ◽  
pp. 1850111 ◽  
Author(s):  
J. J. Ocampo-Hidalgo ◽  
J. Alducín-Castillo ◽  
I. Vázquez-Álvarez ◽  
L. N. Oliva-Moreno ◽  
J. E. Molinar-Solís
Keyword(s):  
High Resistance ◽  
Small Area ◽  
Low Voltage ◽  
Cmos Technology ◽  
Floating Gate ◽  
Process Models ◽  
Cmos Process ◽  
Gain Bandwidth ◽  
Measurement Results ◽  
Improved Performance

A quasi-floating gate (QFG) “super-follower” is presented. The high resistance used by the QFG transistor is constructed by two diodes connected back-to-back, leading to a simple-, temperature-stable- and small-area solution. Expressions for the behavior of the follower are introduced and verified by circuit simulations in LTSPICE using 0.5[Formula: see text][Formula: see text]m CMOS process models, which show an improved performance of the proposed circuit with respect to the original super-follower. To prove the principle, a test cell was fabricated in the same 0.5[Formula: see text][Formula: see text]m CMOS technology and characterized. Measurement results show a gain-bandwidth product of 10[Formula: see text]MHz and power consumption of 120[Formula: see text][Formula: see text]W with a 1.5[Formula: see text]V single supply.

Low Voltage FGMOS Four Quadrants Analog Multiplier

2014 ◽  
Vol 918 ◽  
pp. 313-318
Author(s):  
Jesús de la Cruz-Alejo ◽  
L. Noe Oliva-Moreno
Keyword(s):  
Power Consumption ◽  
Power Supply ◽  
Low Voltage ◽  
Floating Gate ◽  
Cmos Process ◽  
Resistive Load ◽  
Analog Multiplier ◽  
Output Impedance ◽  
Cmos Transistors ◽  
Current Sensors

In this paper a low voltage FGMOS analog multiplier is proposed that uses a follower voltage flipped (FVF), which dominates its operation. In order to reduce the power supply of the multiplier, floating gate CMOS transistors (FGMOS) are used. Theoretical steps of the FVF design are presented together with its simulation. The output of the FVF is insensitive to the device parameters and is loaded with a resistive load. The multiplier design consists of two FVF cells, two current sensors FVF and one Gilbert cell multiplier. The results show that the proposed multiplied in a 0.13μm CMOS process exhibits significant benefits in terms of linearity, insensibility to device parameters, bandwidth and output impedance. The power supply is 0.8V and a power consumption of 181μW.

New Schmitt Trigger with Controllable Hysteresis using Dual Control Gate-Floating Gate Transistor (DCG-FGT)

2013 ◽  
Vol 2 (1) ◽  
pp. 49
Author(s):  
Abderrezak Marzaki ◽  
V. Bidal ◽  
R. Laffont ◽  
W. Rahajandraibe ◽  
J-M. Portal ◽  
...  
Keyword(s):  
Low Voltage ◽  
Schmitt Trigger ◽  
Cmos Technology ◽  
Floating Gate ◽  
Dual Control ◽  
Switching Voltage ◽  
Voltage Range ◽  
Rail To Rail ◽  
Floating Gate Transistor ◽  
Simulation Results

This paper presents different low voltage adjustable CMOS Schmitt trigger using DCG-FGT transistor. Simple circuits are introduced to provide flexibility to program the hysteresic threshold in this paper. The hysteresis can be controlled accurately at a large voltage range. The proposed Schmitt trigger have been designed using 90nm 1.2V CMOS technology and simulated using Eldo with PSP device models. The simulation results show rail-to-rail operation and adjustable switching voltages <em>V<sub>TH- </sub></em>(low switching voltage) and <em>V<sub>TH+ </sub></em>(high switching voltage).

A Self-Starting 70 mV-1 V, 65% Peak Efficient, TEG Energy Harvesting Chip with 5 ms Startup Time

2016 ◽  
Vol 26 (03) ◽  
pp. 1750040
Author(s):  
Arun Kumar Sinha
Keyword(s):  
Peak Power ◽  
Low Voltage ◽  
Input Voltage ◽  
Cmos Technology ◽  
Voltage Source ◽  
Thermo Electric ◽  
Electric Generator ◽  
Measurement Results ◽  
Startup Time ◽  
Work Up

This paper presents design and measurement results of a DC–DC converter, intended to harvest energy from a thermo-electric generator (TEG). The prototype chip was fabricated in 130[Formula: see text]nm CMOS technology. The designed converter can extract maximum power from a TEG, without using an input capacitor ([Formula: see text] or a closed loop maximum peak power tracking circuit to regulate the input voltage ([Formula: see text]. The converter uses a low voltage oscillator coupled with charge pump to directly power the auxiliary circuits; and auxiliary circuits drives two inductors in two half cycles of a clock pulse. The measurement has been performed by using a TEG, and a voltage source (50–200[Formula: see text]mV) with a series resistance of 5[Formula: see text]ohms. The result shows that the prototype can self-starts from 70[Formula: see text]mV with 5[Formula: see text]ms startup time and can work up to a minimum of 50[Formula: see text]mV; and can extract, 57.2% (at 50[Formula: see text]mV) to 65% (at 200[Formula: see text]mV), of the available power.

AN ULTRA LOW-VOLTAGE/POWER-EFFICIENT ALL-DIGITAL DELAY LOCKED LOOP IN 55 nm CMOS TECHNOLOGY

2012 ◽  
Vol 21 (08) ◽  
pp. 1240025 ◽  
Author(s):  
CHUN-YUAN CHENG ◽  
JINN-SHYAN WANG ◽  
CHENG-TAI YEH
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Low Voltage ◽  
Cmos Technology ◽  
Maximum Frequency ◽  
Clock Frequency ◽  
Power Efficient ◽  
Delay Locked Loop ◽  
Measurement Results ◽  
Variation Tolerance

This paper presents an all-digital delay locked loop (ADDLL) that uses asynchronous-deskewing technology and achieves low power/voltage, small jitter, fast locking, and high process, voltage, and temperature (PVT)-variation tolerance. The measurement results show that the maximum frequency is 100 MHz at 0.35 V with 19 μW power dissipation, 62 ps peak-to-peak jitter, and 3 locking cycles. When operated at 0.5 V, the measured maximal operating clock frequency is 450 MHz with 12 ps peak-to-peak jitter, 6 locking cycles and 119 μW power dissipation. The ADDLL is fabricated with 55 nm CMOS technology, and the active area is only 0.019 mm2.

Sub-Volt Fully Balanced Differential Difference Amplifier

2014 ◽  
Vol 24 (01) ◽  
pp. 1550005 ◽  
Author(s):  
Fabian Khateb ◽  
Montree Kumngern ◽  
Spyridon Vlassis ◽  
Costas Psychalinos ◽  
Tomasz Kulej
Keyword(s):  
Low Voltage ◽  
Input Voltage ◽  
Cmos Technology ◽  
Floating Gate ◽  
Voltage Range ◽  
State Variable ◽  
Low Voltage Operation ◽  
Differential Difference Amplifier ◽  
Simulation Results ◽  
State Variable Filter

This paper presents a new CMOS structure for a fully balanced differential difference amplifier (FB-DDA) designed to operate from a sub-volt supply. This structure employs the bulk-driven quasi-floating-gate (BD-QFG) technique to achieve the capability of an ultra-low voltage operation and an extended input voltage range. The proposed BD-QFG FB-DDA is suitable for ultra-low-voltage low-power applications. The circuit is designed with a single supply of 0.5 V and consumes only 357 nW of power. The proposed circuit was simulated in a 0.18-μm TSMC CMOS technology and the simulation results prove its functionality and attractive parameters. An application example of a state variable filter is also presented to confirm the usefulness of the proposed BD-QFG FB-DDA.

CHAOS-BASED MIXED SIGNAL IMPLEMENTATION OF SPIKING NEURONS

2009 ◽  
Vol 19 (06) ◽  
pp. 465-471 ◽  
Author(s):  
JOSEP L. ROSSELLO ◽  
VINCENT CANALS ◽  
ANTONI MORRO ◽  
JAUME VERD
Keyword(s):  
Neural Networks ◽  
Small Area ◽  
Cmos Technology ◽  
Spiking Neurons ◽  
Spiking Neural Networks ◽  
Cmos Process ◽  
Linear Behavior ◽  
Analog Part ◽  
Digital Circuitry ◽  
Analog Circuitry

A new design of Spiking Neural Networks is proposed and fabricated using a 0.35 μm CMOS technology. The architecture is based on the use of both digital and analog circuitry. The digital circuitry is dedicated to the inter-neuron communication while the analog part implements the internal non-linear behavior associated to spiking neurons. The main advantages of the proposed system are the small area of integration with respect to digital solutions, its implementation using a standard CMOS process only and the reliability of the inter-neuron communication.

scholarly journals Robust and Latch-Up-Immune LVTSCR Device with an Embedded PMOSFET for ESD Protection in a 28-nm CMOS Process

2020 ◽  
Vol 15 (1) ◽  
Author(s):  
Ruibo Chen ◽  
Hongxia Liu ◽  
Wenqiang Song ◽  
Feibo Du ◽  
Hao Zhang ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Low Voltage ◽  
Cmos Technology ◽  
Cmos Process ◽  
Triggering Mechanism ◽  
Esd Protection ◽  
Tcad Simulation ◽  
P Type ◽  
28 Nm ◽  
Latch Up

Abstract Low-voltage-triggered silicon-controlled rectifier (LVTSCR) is expected to provide an electrostatic discharge (ESD) protection for a low-voltage integrated circuit. However, it is normally vulnerable to the latch-up effect due to its extremely low holding voltage. In this paper, a novel LVTSCR embedded with an extra p-type MOSFET called EP-LVTSCR has been proposed and verified in a 28-nm CMOS technology. The proposed device possesses a lower trigger voltage of ~ 6.2 V and a significantly higher holding voltage of ~ 5.5 V with only 23% degradation of the failure current under the transmission line pulse test. It is also shown that the EP-LVTSCR operates with a lower turn-on resistance of ~ 1.8 Ω as well as a reliable leakage current of ~ 1.8 nA measured at 3.63 V, making it suitable for ESD protections in 2.5 V/3.3 V CMOS processes. Moreover, the triggering mechanism and conduction characteristics of the proposed device were explored and demonstrated with TCAD simulation.

Silicon Validation of GALS Methods and Architectures in a State-of-the-Art CMOS Process

2014 ◽  
pp. 420-447
Author(s):  
Milos Krstic ◽  
Xin Fan ◽  
Eckhard Grass ◽  
Luca Benini ◽  
M. R. Kakoee ◽  
...  
Keyword(s):  
Cmos Technology ◽  
Design Flow ◽  
Cmos Process ◽  
Special Test ◽  
Interface Circuits ◽  
Future Role ◽  
Measurement Results ◽  
Full Structure ◽  
Point To Point

The GALS methodology has been discussed for many years, but only a few relevant implementations in silicon have been done. This chapter describes the implementation and test of the Moonrake Chip – a complex GALS demonstrator implemented in 40 nm CMOS technology. Two novel types of GALS interface circuits are validated: point-to-point pausible clocking GALS interfaces and GALS NoC interconnects. Point-to-point GALS interfaces are integrated within a complex OFDM baseband transmitter block, and for NoC switches special test structures are defined. This chapter discloses the full structure of the respective interfaces, the complete GALS system, as well as the design flow utilized to implement them on the chip. Moreover, the full set of measurement results are presented, including area, power, and EMI results. Significant benefits and robustness of our applied GALS methodology are shown. Finally, some outlook and vision of the future role of GALS are outlined.

scholarly journals Ultra-Low-Voltage Low-Power Bulk-Driven Quasi-Floating-Gate Operational Transconductance Amplifier

2014 ◽  
Vol 2014 ◽  
pp. 1-7 ◽  
Author(s):  
Ziad Alsibai ◽  
Salma Bay Abo Dabbous
Keyword(s):  
Signal Processing ◽  
Power Consumption ◽  
Low Power ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Bias Current ◽  
Floating Gate ◽  
Operational Transconductance Amplifier ◽  
Transconductance Amplifier

A new ultra-low-voltage (LV) low-power (LP) bulk-driven quasi-floating-gate (BD-QFG) operational transconductance amplifier (OTA) is presented in this paper. The proposed circuit is designed using 0.18 μm CMOS technology. A supply voltage of ±0.3 V and a quiescent bias current of 5 μA are used. The PSpice simulation result shows that the power consumption of the proposed BD-QFG OTA is 13.4 μW. Thus, the circuit is suitable for low-power applications. In order to confirm that the proposed BD-QFG OTA can be used in analog signal processing, a BD-QFG OTA-based diodeless precision rectifier is designed as an example application. This rectifier employs only two BD-QFG OTAs and consumes only 26.8 μW.

A LOW-VOLTAGE LOW-POWER 10-BIT 200 MS/S PIPELINED ADC IN 90 NM CMOS

2010 ◽  
Vol 19 (02) ◽  
pp. 393-405 ◽  
Author(s):  
SAHEL ABDINIA ◽  
MOHAMMAD YAVARI
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Cmos Process ◽  
Pipelined Adc ◽  
Pipeline Adc ◽  
Class A ◽  
Reduction Techniques ◽  
Dynamic Comparators

This paper presents a low-power 10-bit 200 MS/s pipelined ADC in a 90 nm CMOS technology with 1 V supply voltage. To decrease the power dissipation efficiently, a new architecture using a combination of two power reduction techniques named double-sampling and opamp-sharing has been used to reduce the power consumption significantly, without any degradation in the performance of the ADC. In addition, the stage scaling technique has been applied to the ADC efficiently, and two-stage class A/AB and class A amplifiers and dynamic comparators have been used in sample and hold and sub-ADCs. According to HSPICE simulation results, the 10-bit 200 MSample/s pipeline ADC with a 9.375 MHz, 1-VP-P,diff input signal in a 90 nm CMOS process achieves a SNDR of 58.5 dB while consuming only 30.9 mW power from a 1 V supply voltage.

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