ON THE DESIGN OF ADAPTIVE-BANDWIDTH ALL-DIGITAL PHASE-LOCKED LOOPS

2011 ◽  
Vol 20 (06) ◽  
pp. 1037-1049 ◽  
Author(s):  
YAWGENG A. CHAU ◽  
CHEN-FENG CHEN
Keyword(s):  
Design Procedure ◽  
Design Criterion ◽  
Phase Locked Loops ◽  
Input Frequency ◽  
Digital Phase ◽  
Loop Bandwidth ◽  
Adaptive Bandwidth ◽  
Lock In ◽  
Reference Input ◽  
Time Analogy

The second-order adaptive-bandwidth all-digital phase-locked loop (ADB-ADPLL) is designed and analyzed by using a new design procedure. Based on a discrete-time analogy of a continuous-time PLL (CTPLL) with the z-transform, the design criterion of the ADB-ADPLL is derived and a design procedure is developed. Following the design criterion, the ADB-ADPLL can adapt its system parameters to balance the loop noise bandwidth and lock-in time. According to the design criterion, the ratio of the loop bandwidth to the reference input frequency can be maintained as a constant if the sampling frequency is a fixed multiplier of the input frequency. An example is given to illustrate the design procedure and simulation results are presented to validate the adaptive characteristics with respect to the phase noise and varying bands of input frequency.

scholarly journals A Low-Power Digitally Controlled Oscillator for All Digital Phase-Locked Loops

VLSI Design ◽  
2010 ◽  
Vol 2010 ◽  
pp. 1-11 ◽  
Author(s):  
Jun Zhao ◽  
Yong-Bin Kim
Keyword(s):  
Low Power ◽  
Supply Voltage ◽  
Schmitt Trigger ◽  
Ring Oscillator ◽  
Phase Locked Loops ◽  
Digital Phase ◽  
Digitally Controlled ◽  
Low Power Cmos ◽  
Digitally Controlled Oscillator ◽  
Lock In

A low-power and low-jitter 12-bit CMOS digitally controlled oscillator (DCO) design is presented. The Low-Power CMOS DCO is designed based on the ring oscillator implemented with Schmitt trigger inverters. The proposed DCO circuit uses control codes of thermometer type to reduce jitters. Performance of the DCO is verified through a novel All Digital Phase-Locked Loop (ADPLL) designed with a unique lock-in process by employing a time-to-digital converter, where both the frequency of the reference clock and the delay between DCO_output and DCO_clock is measured. A carefully designed reset process reduces the phase acquisition process to two cycles. The ADPLL was implemented using the 32 nm Predictive Technology Model (PTM) at 0.9 V supply voltage, and the simulation results show that the proposed ADPLL achieves 10 and 2 reference cycles of frequency and phase acquisitions, respectively, at 700 MHz with less than 67 ps peak-to-peak jitter. The DCO consumes 2.2 mW at 650 MHz with 0.9 V power supply.

scholarly journals Computation of the lock-in ranges of phase-locked loops with PI filter

2016 ◽  
Vol 49 (14) ◽  
pp. 36-41 ◽  
Author(s):  
Konstantin D. Aleksandrov ◽  
Nikolay V. Kuznetsov ◽  
Gennady A. Leonov ◽  
Pekka Neittaanmäki ◽  
Marat V. Yuldashev ◽  
...  
Keyword(s):  
Phase Locked Loops ◽  
Lock In

Paper 7: Review of Porous Metal Bearing Developments

1965 ◽  
Vol 180 (11) ◽  
pp. 154-159
Author(s):  
P. R. Marshall ◽  
V. T. Morgan
Keyword(s):  
Hydrodynamic Lubrication ◽  
Design Procedure ◽  
Porous Metal ◽  
Design Criterion ◽  
Gas Content ◽  
Low Permeability ◽  
Eccentricity Ratio ◽  
Practical Design ◽  
Recent Developments ◽  
And Performance

Recent developments aimed at increasing the life and performance of porous metal bearings have included a double layer bearing of low permeability, porous aluminium for better heat conductivity, ultrasonic cleaning of the porous surface, and the possible use of synthetic oils for improved oxidation resistance. The interactions between the porosity and the oil in terms of the surface tension, the effects of gas content on viscosity and permeability, and the rate of oil loss and reabsorption, are discussed in relation to these developments. A better understanding of the mechanisms involved leads to a practical design criterion for the limit of hydrodynamic lubrication of porous bearings of finite L/d ratio based on an eccentricity ratio of 0.8 and the difficulties of determining the appropriate value of permeability required for a more rigorous design procedure are outlined, together with suggested work for overcoming them.

Inexpensive lock-in amplifiers based on integrated circuit phase-locked loops

1975 ◽  
Vol 47 (2) ◽  
pp. 363-366 ◽  
Author(s):  
Gary. Horlick ◽  
Keith R. Betty
Keyword(s):  
Integrated Circuit ◽  
Phase Locked Loops ◽  
Lock In
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