A Dual Band Fractional-N Frequency Synthesizer with a Self-Calibrated Charge Pump for WLAN Standards

2018 ◽  
Vol 27 (08) ◽  
pp. 1850131 ◽  
Author(s):  
Mostafa Azadbakht ◽  
Ali Sahafi ◽  
Esmaeil Najafi Aghdam
Keyword(s):  
Ieee 802.11 ◽  
Power Dissipation ◽  
Frequency Synthesizer ◽  
Charge Pump ◽  
Local Oscillator ◽  
Cmos Technology ◽  
Dual Band ◽  
Spectral Purity ◽  
Fully Integrated ◽  
Voltage Range

This work presents a fully integrated fractional-[Formula: see text] frequency synthesizer that covers the entire frequency bands specified in the IEEE 802.11 a/b/g/n. In this paper, the effects of charge pump (CP) gain mismatch on spectral purity of local oscillator signal is studied theoretically and a new high precision self-calibrated CP is presented for alleviating the nonidealities. The idea is implemented in a 0.18-[Formula: see text]m standard CMOS technology. According to post layout simulation, the proposed calibration circuit demonstrates an excellent matching in the CP currents in a wide voltage range. By using this technique, the average of close-in phase noise of the designed frequency synthesizer is suppressed by more than 12[Formula: see text]dBc. The active whole chip die area is 0.475[Formula: see text]mm2 and the power dissipation from a 1.8-V DC supply is 17.3–20.6[Formula: see text]mW.

A Fully Integrated Dual-Band Low Noise Amplifier For IEEE 802.11 & Hiperlan Applications

2004 ◽  
Vol 1 (1) ◽  
pp. 26-32 ◽  
Author(s):  
Mou Shouxian ◽  
Ma Jianguo ◽  
Yeo Kiat Seng ◽  
Do Man
Keyword(s):  
Ieee 802.11 ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Dual Band ◽  
Fully Integrated ◽  
Noise Amplifier

Low Power, Wide Range Synthesizer for 534MHz–18.56GHz Band with FoM of −192.45dBc/Hz

2021 ◽  
pp. 2250032
Author(s):  
Gaurav Kumar Sharma ◽  
Arun Kishor Johar ◽  
D. Boolchandani
Keyword(s):  
Figure Of Merit ◽  
Satellite Communication ◽  
Frequency Synthesizer ◽  
Supply Voltage ◽  
Wide Spectrum ◽  
Charge Pump ◽  
Cmos Technology ◽  
Ring Oscillator ◽  
Loop Filter ◽  
Wide Range

A wide range frequency synthesizer is designed with the help of dual voltage tunable Differential Ring Oscillator (DRO). Frequency ranging from 534[Formula: see text]MHz to 18.56[Formula: see text]GHz can be generated using the proposed synthesizer. As proposed circuit utilizes dual voltage tunable DRO, a select input is provided to control the output frequency range. Logic low value (0[Formula: see text]V) of select input generates frequencies from 534[Formula: see text]MHz to 5.08[Formula: see text]GHz whereas logic high value (1.1[Formula: see text]V) of select input enables the frequency generation in the range of 5.08[Formula: see text]GHz to 18.56[Formula: see text]GHz. This work utilizes a single charge pump and single loop filter along with charge pump and bias control circuit. Proposed circuit is designed in GPDK 45-nm CMOS technology with supply voltage of 1.1[Formula: see text]V. Power consumption of the proposed circuits is 2.88[Formula: see text]mW while generating frequency of 7.84[Formula: see text]GHz. Proposed synthesizer demonstrates Figure of Merit (FoM2) of [Formula: see text][Formula: see text]dBc/Hz at this frequency. Because of such a wide spectrum, this synthesizer is well suited in the field of satellite communication, GPS and navigation.

Comparison frequency doubling and charge pump matching techniques for dual-band /spl Delta//spl Sigma/ fractional-N frequency synthesizer

2005 ◽  
Vol 40 (11) ◽  
pp. 2228-2236 ◽  
Author(s):  
Hyungki Huh ◽  
Yido Koo ◽  
Kang-Yoon Lee ◽  
Yeonkyeong Ok ◽  
Sungho Lee ◽  
...  
Keyword(s):  
Frequency Synthesizer ◽  
Frequency Doubling ◽  
Charge Pump ◽  
Dual Band ◽  
Matching Techniques

A Fully-Integrated D-Band Frequency Synthesizer in 0.13-μm SiGe BiCMOS

2015 ◽  
Vol 25 (01) ◽  
pp. 1640010
Author(s):  
Jin He ◽  
Yong-Zhong Xiong ◽  
Jiankang Li ◽  
Muthukumaraswamy Annamalai Arasu ◽  
Yue Ping Zhang
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Frequency Synthesizer ◽  
Frequency Multiplier ◽  
Band Frequency ◽  
Chip Area ◽  
Fully Integrated ◽  
Bicmos Technology ◽  
Sige Bicmos ◽  
Low Power Dissipation

This paper presents a fully-integrated D-band frequency synthesizer (FS) in 0.13-[Formula: see text]m SiGe BiCMOS technology. The proposed FS consists of a 20-GHz phase-locked loop (PLL) and a frequency multiplier including a doubler ([Formula: see text][Formula: see text]2) and a quadrupler ([Formula: see text][Formula: see text]4). The FS generates the D-band output signals from 164.08 to 166.19[Formula: see text]GHz. At 166.19[Formula: see text]GHz, the measured phase noises (PN) at 100-kHz and 1-MHz offset frequencies are [Formula: see text]54.07[Formula: see text]dBc/Hz and [Formula: see text]72.29[Formula: see text]dBc/Hz, respectively. The proposed FS achieves the low power dissipation of around 110[Formula: see text]mW and the chip area is [Formula: see text] including all testing pads. The FS has great potential to be used for low-power D-band applications.

Towards the Design of Cost-efficient Generic Register Using Quantum-dot Cellular Automata

2020 ◽  
Vol 10 (4) ◽  
pp. 534-547
Author(s):  
Chiradeep Mukherjee ◽  
Saradindu Panda ◽  
Asish K. Mukhopadhyay ◽  
Bansibadan Maji
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Power Dissipation ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Digital Data ◽  
Design Parameters ◽  
Flip Flop ◽  
Quantum Dot Cellular Automata ◽  
Cost Efficient

Background: The advancement of VLSI in the application of emerging nanotechnology explores quantum-dot cellular automata (QCA) which has got wide acceptance owing to its ultra-high operating speed, extremely low power dissipation with a considerable reduction in feature size. The QCA architectures are emerging as a potential alternative to the conventional complementary metal oxide semiconductor (CMOS) technology. Experimental: Since the register unit has a crucial role in digital data transfer between the electronic devices, such study leading to the design of cost-efficient and highly reliable QCA register is expected to be a prudent area of research. A thorough survey on the existing literature shows that the generic models of Serial-in Serial Out (SISO), Serial-in-Parallel-Out (SIPO), Parallel-In- Serial-Out (PISO) and Parallel-in-Parallel-Out (PIPO) registers are inadequate in terms of design parameters like effective area, delay, O-Cost, Costα, etc. Results: This work introduces a layered T gate for the design of the D flip flop (LTD unit), which can be broadly used in SISO, SIPO, PISO, and PIPO register designs. For detection and reporting of high susceptible errors and defects at the nanoscale, the reliability and defect tolerant analysis of LTD unit are also carried out in this work. The QCA design metrics for the general register layouts using LTD unit is modeled. Conclusion: Moreover, the cost metrics for the proposed LTD layouts are thoroughly studied to check the functional complexity, fabrication difficulty and irreversible power dissipation of QCA register layouts.

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