A Full-Wave CMOS Rectifier with High-Speed Comparators for Implantable Medical Devices

2019 ◽  
Vol 28 (11) ◽  
pp. 1950178
Author(s):  
Mahnaz Janipoor Deylamani ◽  
Fatemeh Abdi ◽  
Parviz Amiri
Keyword(s):  
Conversion Efficiency ◽  
Medical Devices ◽  
Power Efficiency ◽  
High Speed ◽  
Cmos Technology ◽  
Voltage Source ◽  
Conduction Time ◽  
High Power Conversion Efficiency ◽  
Implantable Medical Devices ◽  
Full Wave

In this paper, we present a CMOS full-wave rectifier with comparator-controlled switches for transmission of wireless power in implantable medical devices. It uses MOS transistors as low loss switches to provide high power conversion efficiency (PCE). The proposed fast comparator circuit, by controlling the switches in the rectifier, reduces the reverse leakage current in the negative cycle and increases the conduction time in the positive cycle so that more current flows into the output load and optimizes the rectifier power efficiency. The designed comparator does not require constant voltage source for its function and it is self-biased. The proposed rectifier is implemented using 0.18[Formula: see text][Formula: see text]m CMOS technology and provides 1.195[Formula: see text]V output DC voltage with a 190[Formula: see text][Formula: see text] load resistance and AC input signal with the frequency of 13.56[Formula: see text]MHz and peak-to-peak amplitude of 1.36[Formula: see text]V. Under these conditions, PCE and voltage conversion efficiency (VCE) values are 85.5% and 88%, respectively. The peak PCE and VCE increase with a decrease in operation frequency and dimensions of transistors are optimized using multiple simulations for intended frequency.

LP-HS Logic Evaluation on TSMC 0.18μm CMOS Technology

2017 ◽  
Vol 26 (04) ◽  
pp. 1740024
Author(s):  
Aloke Saha ◽  
Sushil Kumar ◽  
Debajit Das ◽  
Mrinmoy Chakraborty
Keyword(s):  
Power Efficiency ◽  
High Speed ◽  
Building Blocks ◽  
Cmos Technology ◽  
Worst Case ◽  
Temperature Variations ◽  
Noise Margin ◽  
Reliability Issue ◽  
Logic Threshold ◽  
System Focus

Present paper analyses different aspects of “Low Power-High Speed” (LP-HS) logic in favour of present day ULSI system focus. At first, the speed-power efficiency of LP-HS logic is investigated by designing some basic digital building blocks like Buffer, OR, AND, XOR etc. Next, the Voltage Transfer Characteristics (VTC), Noise Margin (NM) and the temperature effect on logic threshold with respect to LP-HS Buffer circuit are examined. The robustness and reliability of LP-HS Logic has been measured in terms of corner analysis with TT (Typical), FF (Fastest) and SS (Slowest) PVT (Process Voltage Temperature) variations on LP-HS XOR circuit. The worst case delay and PDP variation is recorded. Finally the 8:1 Multiplexer is designed, optimized and evaluated based on LP-HS Logic. The evaluated results are compared with some recent competitive designs to benchmark. To resolve reliability issue the corner analysis with PVT variation has been performed on designed 8:1 Multiplexor circuit. All the simulations are done on TSMC 0.18μm CMOS technology using Tanner EDA V.13 at 25°C temperature with 1.8V supply rail.

scholarly journals A Review of Power Management Integrated Circuits for Ultrasound-Based Energy Harvesting in Implantable Medical Devices

2021 ◽  
Vol 11 (6) ◽  
pp. 2487
Author(s):  
Andrea Ballo ◽  
Michele Bottaro ◽  
Alfio Dario Grasso
Keyword(s):  
Energy Harvesting ◽  
Power Management ◽  
Medical Devices ◽  
Power Efficiency ◽  
Building Blocks ◽  
Design Guidelines ◽  
Power Budget ◽  
Implantable Medical Devices ◽  
Piezoelectric Energy ◽  
Piezoelectric Devices

This paper aims to review the recent architectures of power management units for ultrasound-based energy harvesting, while focusing on battery-less implantable medical devices. In such systems, energy sustainability is based on piezoelectric devices and a power management circuit, which represents a key building block since it maximizes the power extracted from the piezoelectric devices and delivers it to the other building blocks of the implanted device. Since the power budget is strongly constrained by the dimension of the piezoelectric energy harvester, complexity of topologies have been increased bit by bit in order to achieve improved power efficiency also in difficult operative conditions. With this in mind, the introduced work consists of a comprehensive presentation of the main blocks of a generic power management unit for ultrasound-based energy harvesting and its operative principles, a review of the prior art and a comparative study of the performance achieved by the considered solutions. Finally, design guidelines are provided, allowing the designer to choose the best topology according to the given design specifications and technology adopted.

scholarly journals A Hidden DCT-Based Invisible Watermarking Method for Low-Cost Hardware Implementations

Electronics ◽  
2021 ◽  
Vol 10 (12) ◽  
pp. 1465
Author(s):  
Yuxuan Wang ◽  
Yuanyong Luo ◽  
Zhongfeng Wang ◽  
Hongbing Pan
Keyword(s):  
Resource Sharing ◽  
Power Efficiency ◽  
High Speed ◽  
Low Cost ◽  
Color Space ◽  
Computational Cost ◽  
Cmos Technology ◽  
Hardware Implementations ◽  
Invisible Watermarking ◽  
Speed Performance

This paper presents an invisible and robust watermarking method and its hardware implementation. The proposed architecture is based on the discrete cosine transform (DCT) algorithm. Novel techniques are applied as well to reduce the computational cost of DCT and color space conversion to achieve low-cost and high-speed performance. Besides, a watermark embedder and a blind extractor are implemented in the same circuit using a resource-sharing method. Our approach is compatible with various watermarking embedding ratios, such as 1/16 and 1/64, with a PSNR of over 45 and the NC value of 1. After Joint Photographic Experts Group (JPEG) compression with a quality factor (QF) of 50, our method can achieve an NC value of 0.99. Results from a design compiler (DC) with TSMC-90 nm CMOS technology show that our design can achieve the frequency of 2.32 GHz with the area consumption of 304,980.08 μm2 and power consumption of 508.1835 mW. For the FPGA implementation, our method achieved a frequency of 421.94 MHz. Compared with the state-of-the-art works, our design improved the frequency by 4.26 times, saved 90.2% on area and increased the power efficiency by more than 1000 fold.

scholarly journals High-speed multicarrier transmission scheme for implantable medical devices

2011 ◽  
Vol 8 (3) ◽  
pp. 143-148
Author(s):  
Junha Im ◽  
Yunho Jung ◽  
Seongjoo Lee ◽  
Jaeseok Kim
Keyword(s):  
Medical Devices ◽  
High Speed ◽  
Transmission Scheme ◽  
Implantable Medical Devices ◽  
Multicarrier Transmission

scholarly journals A 16 Gbps, Full-Duplex Transceiver over Lossy On-Chip Interconnects in 28 nm CMOS Technology

Electronics ◽  
2020 ◽  
Vol 9 (5) ◽  
pp. 717
Author(s):  
Arash Ebrahimi Jarihani ◽  
Sahar Sarafi ◽  
Michael Koeberle ◽  
Johannes Sturm ◽  
Andrea M. Tonello
Keyword(s):  
Power Efficiency ◽  
High Speed ◽  
Supply Voltage ◽  
Impedance Matching ◽  
Low Complexity ◽  
Cmos Technology ◽  
Data Rate ◽  
Full Duplex ◽  
On Chip ◽  
28 Nm

A high-speed full-duplex transceiver (FDT) over lossy on-chip interconnects is presented. The FDT employs a hybrid circuit to separate the inbound and outbound signals from each other and also performs echo-cancellation with the help of the main and the auxiliary drivers. A hybrid MOS device is utilized for impedance matching and conversion of the received voltage signal into a current signal for amplification. Moreover, a compensation capacitance ( C c ) is used at the output of the main driver to minimize the residual echo signal and achieve a higher data rate. The entire FDT architecture has been designed in TSMC 28 nm CMOS standard process with 0.9 V supply voltage. The performance results validate a 16 Gbps FD operation with a root-mean-square (RMS) jitter of 16.4 ps, and a power efficiency of 0.16 pJ/b/mm over a 5 mm on-chip interconnect without significant effect due to process-voltage-temperature (PVT) variations. To the best knowledge of the authors, this work shows the highest achievable full-duplex data rate, among the solutions reported in the literature to date, yet with low complexity, low layout area of 1581 μ m 2 and competitive power efficiency.

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