scholarly journals A Hidden DCT-Based Invisible Watermarking Method for Low-Cost Hardware Implementations

Electronics ◽  
2021 ◽  
Vol 10 (12) ◽  
pp. 1465
Author(s):  
Yuxuan Wang ◽  
Yuanyong Luo ◽  
Zhongfeng Wang ◽  
Hongbing Pan
Keyword(s):  
Resource Sharing ◽  
Power Efficiency ◽  
High Speed ◽  
Low Cost ◽  
Color Space ◽  
Computational Cost ◽  
Cmos Technology ◽  
Hardware Implementations ◽  
Invisible Watermarking ◽  
Speed Performance

This paper presents an invisible and robust watermarking method and its hardware implementation. The proposed architecture is based on the discrete cosine transform (DCT) algorithm. Novel techniques are applied as well to reduce the computational cost of DCT and color space conversion to achieve low-cost and high-speed performance. Besides, a watermark embedder and a blind extractor are implemented in the same circuit using a resource-sharing method. Our approach is compatible with various watermarking embedding ratios, such as 1/16 and 1/64, with a PSNR of over 45 and the NC value of 1. After Joint Photographic Experts Group (JPEG) compression with a quality factor (QF) of 50, our method can achieve an NC value of 0.99. Results from a design compiler (DC) with TSMC-90 nm CMOS technology show that our design can achieve the frequency of 2.32 GHz with the area consumption of 304,980.08 μm2 and power consumption of 508.1835 mW. For the FPGA implementation, our method achieved a frequency of 421.94 MHz. Compared with the state-of-the-art works, our design improved the frequency by 4.26 times, saved 90.2% on area and increased the power efficiency by more than 1000 fold.

scholarly journals Lead Selenide Polycrystalline Coatings Sensitized Using Diffusion and Ion Beam Methods for Uncooled Mid-Infrared Photodetection

Coatings ◽  
2018 ◽  
Vol 8 (12) ◽  
pp. 444 ◽  
Author(s):  
Hao Yang ◽  
Xiaojiang Li ◽  
Guodong Wang ◽  
Jianbang Zheng
Keyword(s):  
High Speed ◽  
Large Scale ◽  
Low Cost ◽  
Ion Beam ◽  
Lead Selenide ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Recombination Suppression ◽  
Mid Infrared ◽  
Physical Effects

Polycrystalline lead selenide material that is processed after a sensitization technology offers the additional physical effects of carrier recombination suppression and carrier transport manipulation, making it sufficiently sensitive to mid-infrared radiation at room temperature. Low-cost and large-scale integration with existing electronic platforms such as complementary metal–oxide–semiconductor (CMOS) technology and multi-pixel readout electronics enable a photodetector based on polycrystalline lead selenide coating to work in high-speed, low-cost, and low-power consumption applications. It also shows huge potential to compound with other materials or structures, such as the metasurface for novel optoelectronic devices and more marvelous properties. Here, we provide an overview and evaluation of the preparations, physical effects, properties, and potential applications, as well as the optoelectronic enhancement mechanism, of lead selenide polycrystalline coatings.

A Low-Cost Highly Reliable Spintronic True Random Number Generator Circuit for Secure Cryptography

SPIN ◽  
2019 ◽  
Vol 10 (01) ◽  
pp. 2050003 ◽  
Author(s):  
Iman Alibeigi ◽  
Abdolah Amirany ◽  
Ramin Rajaei ◽  
Mahmoud Tabandeh ◽  
Saeed Bagheri Shouraki
Keyword(s):  
High Speed ◽  
High Performance ◽  
Random Number ◽  
Low Cost ◽  
Random Number Generator ◽  
Magnetic Tunnel Junction ◽  
Random Number Generation ◽  
Cmos Technology ◽  
Random Numbers ◽  
Number Generation

Generation of random numbers is one of the most important steps in cryptographic algorithms. High endurance, high performance and low energy consumption are the attractive features offered by the Magnetic Tunnel Junction (MTJ) devices. Therefore, they have been considered as one of the promising candidates for next-generation digital integrated circuits. In this paper, a new circuit design for true random number generation using MTJs is proposed. Our proposed circuit offers a high speed, low power and a truly random number generation. In our design, we employed two MTJs that are configured in special states. Generated random bit at the output of the proposed circuit is returned to the write circuit to be written in the relevant cell for the next random generation. In a random bitstream, all bits must have the same chance of being “0”or “1”. We have proposed a new XOR-based method in this paper to resolve this issue in multiple random generators that produce truly random numbers with a different number of ones and zeros in the output stream. The simulation results using a 45[Formula: see text]nm CMOS technology with a special model of MTJ validated the advantages offered by the proposed circuit.

High Speed Min/Max Architecture Based on a Novel Comparator in 0.18-μm CMOS Process

2015 ◽  
Vol 24 (04) ◽  
pp. 1550048 ◽  
Author(s):  
Amir Fathi ◽  
Abdollah Khoei ◽  
Khayrollah Hadidi
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Current Mode ◽  
Cmos Technology ◽  
Operating Frequency ◽  
Cmos Process ◽  
Fuzzy Logic Controllers ◽  
Speed Performance ◽  
External Clock ◽  
Frequency Feature

This paper describes the design of a high speed min/max architecture based on a new current comparator. The main advantage of the proposed circuit which employs a novel preamplifier-latch comparator is the higher operating frequency feature in comparison with previous works. Because the comparator can work in voltage mode, the min/max structure can be redesigned either in voltage or current mode. The designed comparator is refreshed without any external clock. Therefore, it does not degrade the speed performance of proposed min/max structure. These features along with low power consumption qualify the proposed architecture to be widely used in high speed fuzzy logic controllers (FLCs). Post-layout simulation results confirm 3.4 GS/s comparison rate with 9-bit resolution for a 0.9 V peak-to-peak input signal range for the comparator and 800 MHz operating frequency for min/max circuit. The power consumption of whole structure is 912 μW from a 1.8 V power supply using TSMC 0.18-μm CMOS technology.

scholarly journals A low-voltage CMOS current-mode incremental signaling scheme for high-speed parallel links

2021 ◽  
Author(s):  
Tao Wang
Keyword(s):  
High Speed ◽  
Low Voltage ◽  
Low Cost ◽  
Current Mode ◽  
Cmos Technology ◽  
Fully Differential ◽  
Parallel Links ◽  
Data Links ◽  
Parallel Data ◽  
The Cost

Point-to-point parallel links are widly used in short-distance high-speed data communications. For these links, the design goal is not only to integrate a large number of I/Os in the systems, but also to increase the bit rate per I/O. The cost per I/O has to be kept low as performance improves. Voltage and timing error sources limit the performance of data links and affect its robustnest. These kinds of noise impose greater challenges in parallel data links, such as inter-signal timing skew and inter-signal cross-talk. The use of low-cost schemes, such as single-ended signaling, is effected signaficantly [sic] by the voltage and timging [sic] noise. Fully differential signaling schemes, two physical paths per signal channel, significantly increases the cost of system. Therefore, overcoming the voltage noise, keeping the cost low are two challenges in high-speed parallel links. In this thesis, we propose a new current-mode signaling scheme current-mode incremtnal [sic] signaling for high-speed parallel links. Also, the circuits of the receiver called current-integrating receiver are presented. To assess the effectiveness of the proposed signaling scheme, a 4-bit parallel link consisting of four bipolar current-mode drivers, five 10 cm microstrip lines with a FR4 substrate, and four proposed current-integrating receivers is implemented in UMC 0.13[micro]m, 1.2V CMOS technology and analyzed using SpectreRF from Cadence Design Systems with BSIM3V3 device models. Simulation results demonstrate that the proposed current-mode incremental signaling scheme and the current-integrating receiver are capable of transmitting parallel data at 2.5 Gbyte/s.

scholarly journals An Efficient Hardware Architecture with Adjustable Precision and Extensible Range to Implement Sigmoid and Tanh Functions

Electronics ◽  
2020 ◽  
Vol 9 (10) ◽  
pp. 1739
Author(s):  
Hui Chen ◽  
Lin Jiang ◽  
Heping Yang ◽  
Zhonghai Lu ◽  
Yuxiang Fu ◽  
...  
Keyword(s):  
High Speed ◽  
Cmos Technology ◽  
Network Algorithms ◽  
Rotation Mode ◽  
Hardware Implementations ◽  
Vector Mode ◽  
First Time ◽  
Special Case ◽  
Sigmoid Functions ◽  
Case Based

The efficient and precise hardware implementations of tanh and sigmoid functions play an important role in various neural network algorithms. Different applications have different requirements for accuracy. However, it is difficult for traditional methods to achieve adjustable precision. Therefore, we propose an efficient-hardware, adjustable-precision and high-speed architecture to implement them for the first time. Firstly, we present two methods to implement sigmoid and tanh functions. One is based on the rotation mode of hyperbolic CORDIC and the vector mode of linear CORDIC (called RHC-VLC), another is based on the carry-save method and the vector mode of linear CORDIC (called CSM-VLC). We validate the two methods by MATLAB and RTL implementations. Synthesized under the TSMC 40 nm CMOS technology, we find that a special case AR∣VR(3,0), based on RHC-VLC method, has the area of 4290.98 μm2 and the power of 1.69 mW at the frequency of 1.5 GHz. However, under the same frequency, AR∣VC(3) (a special case based on CSM-VLC method) costs 3196.36 μm2 area and 1.38 mW power. They are both superior to existing methods for implementing such an architecture with adjustable precision.

scholarly journals Non-Linear Mathematical Modelling for Phase Locked Loop

2018 ◽  
Vol 7 (4.10) ◽  
pp. 81
Author(s):  
Prithiviraj R ◽  
Selvakumar J
Keyword(s):  
High Speed ◽  
Linear Models ◽  
Low Cost ◽  
Phase Error ◽  
Phase Locked Loop ◽  
Cmos Technology ◽  
Low Noise ◽  
Voltage Controlled Oscillator ◽  
Loop Filter ◽  
Non Linear

Design of Phase Locked Loop (PLL) plays a vital role in transceiver field. Phase Locked Loop comprises of three blocks, namely Phase and frequency detector, loop filter and voltage-controlled oscillator. The greater advancements in CMOS technology such as high frequency, high speed, low noise and phase error leads to low-cost PLL This work aims to develop higher order non-linear models of general Phase Locked Loop. The condition of stability and choice of loop filter is also determined. Based on the analysis, the transfer function for PLL is determined.  

scholarly journals A low-voltage CMOS current-mode incremental signaling scheme for high-speed parallel links

2021 ◽  
Author(s):  
Tao Wang
Keyword(s):  
High Speed ◽  
Low Voltage ◽  
Low Cost ◽  
Current Mode ◽  
Cmos Technology ◽  
Fully Differential ◽  
Parallel Links ◽  
Data Links ◽  
Parallel Data ◽  
The Cost

Point-to-point parallel links are widly used in short-distance high-speed data communications. For these links, the design goal is not only to integrate a large number of I/Os in the systems, but also to increase the bit rate per I/O. The cost per I/O has to be kept low as performance improves. Voltage and timing error sources limit the performance of data links and affect its robustnest. These kinds of noise impose greater challenges in parallel data links, such as inter-signal timing skew and inter-signal cross-talk. The use of low-cost schemes, such as single-ended signaling, is effected signaficantly [sic] by the voltage and timging [sic] noise. Fully differential signaling schemes, two physical paths per signal channel, significantly increases the cost of system. Therefore, overcoming the voltage noise, keeping the cost low are two challenges in high-speed parallel links. In this thesis, we propose a new current-mode signaling scheme current-mode incremtnal [sic] signaling for high-speed parallel links. Also, the circuits of the receiver called current-integrating receiver are presented. To assess the effectiveness of the proposed signaling scheme, a 4-bit parallel link consisting of four bipolar current-mode drivers, five 10 cm microstrip lines with a FR4 substrate, and four proposed current-integrating receivers is implemented in UMC 0.13[micro]m, 1.2V CMOS technology and analyzed using SpectreRF from Cadence Design Systems with BSIM3V3 device models. Simulation results demonstrate that the proposed current-mode incremental signaling scheme and the current-integrating receiver are capable of transmitting parallel data at 2.5 Gbyte/s.

LP-HS Logic Evaluation on TSMC 0.18μm CMOS Technology

2017 ◽  
Vol 26 (04) ◽  
pp. 1740024
Author(s):  
Aloke Saha ◽  
Sushil Kumar ◽  
Debajit Das ◽  
Mrinmoy Chakraborty
Keyword(s):  
Power Efficiency ◽  
High Speed ◽  
Building Blocks ◽  
Cmos Technology ◽  
Worst Case ◽  
Temperature Variations ◽  
Noise Margin ◽  
Reliability Issue ◽  
Logic Threshold ◽  
System Focus

Present paper analyses different aspects of “Low Power-High Speed” (LP-HS) logic in favour of present day ULSI system focus. At first, the speed-power efficiency of LP-HS logic is investigated by designing some basic digital building blocks like Buffer, OR, AND, XOR etc. Next, the Voltage Transfer Characteristics (VTC), Noise Margin (NM) and the temperature effect on logic threshold with respect to LP-HS Buffer circuit are examined. The robustness and reliability of LP-HS Logic has been measured in terms of corner analysis with TT (Typical), FF (Fastest) and SS (Slowest) PVT (Process Voltage Temperature) variations on LP-HS XOR circuit. The worst case delay and PDP variation is recorded. Finally the 8:1 Multiplexer is designed, optimized and evaluated based on LP-HS Logic. The evaluated results are compared with some recent competitive designs to benchmark. To resolve reliability issue the corner analysis with PVT variation has been performed on designed 8:1 Multiplexor circuit. All the simulations are done on TSMC 0.18μm CMOS technology using Tanner EDA V.13 at 25°C temperature with 1.8V supply rail.

The Computational Paradigm of Cellular Automata in Crowd Evacuation

2015 ◽  
Vol 26 (07) ◽  
pp. 851-872 ◽  
Author(s):  
Georgios Ch. Sirakoulis
Keyword(s):  
Cellular Automata ◽  
Real World ◽  
Queuing Theory ◽  
High Speed ◽  
Low Cost ◽  
Computational Cost ◽  
Simulation Models ◽  
Pedestrian Dynamics ◽  
Crowd Management ◽  
Crowd Evacuation

During last decades, Cellular Automata (CAs) as bio-inspired parallel computational tools have been proven rather efficient and robust on modeling and simulating many different physical processes and systems and solving scientific problems, in which global behavior arises from the collective effect of simple components that interact locally. Among others of most renowned and well established CA applications, crowd evacuation and pedestrian dynamics are considered ones of the most timely and lively topics. Numerous models and computational paradigms of CAs either as standalone models or coupled with other theoretical and practical modeling approaches have been introduced in literature. All these crowd models are taking advantage of the fact that CA show evidence of a macroscopic nature with microscopic extensions, i.e. they provide adequate details in the description of human behavior and interaction, whilst they retain the computational cost at low levels. In this aspect, several CA models for crowd evacuation focusing on different modeling principles, like potential fields techniques, obstacle avoidance, follow the leader principles, grouping and queuing theory, long memory effects, etc. are presented in this paper. Moreover, having in mind the inherent parallelism of CA and their straightforward implementation in hardware, some anticipative crowd management systems based on CAs are also shown when operating on medium density crowd evacuation for indoor and outdoor environments. Real world cases and different environments were examined proving the efficiency of the proposed CA based anticipative systems. The proposed hardware implementation of the CAs-based crowd simulation models is advantageous in terms of low-cost, high-speed, compactness and portability features. Finally, robot guided evacuation with the help of CAs is also presented. The proposed framework relies on the well established CAs simulation models, while it employs a real-world evacuation implementation assisted by a mobile robotic guide, which in turn guides people towards a less congestive exit at a time.

scholarly journals A 16 Gbps, Full-Duplex Transceiver over Lossy On-Chip Interconnects in 28 nm CMOS Technology

Electronics ◽  
2020 ◽  
Vol 9 (5) ◽  
pp. 717
Author(s):  
Arash Ebrahimi Jarihani ◽  
Sahar Sarafi ◽  
Michael Koeberle ◽  
Johannes Sturm ◽  
Andrea M. Tonello
Keyword(s):  
Power Efficiency ◽  
High Speed ◽  
Supply Voltage ◽  
Impedance Matching ◽  
Low Complexity ◽  
Cmos Technology ◽  
Data Rate ◽  
Full Duplex ◽  
On Chip ◽  
28 Nm

A high-speed full-duplex transceiver (FDT) over lossy on-chip interconnects is presented. The FDT employs a hybrid circuit to separate the inbound and outbound signals from each other and also performs echo-cancellation with the help of the main and the auxiliary drivers. A hybrid MOS device is utilized for impedance matching and conversion of the received voltage signal into a current signal for amplification. Moreover, a compensation capacitance ( C c ) is used at the output of the main driver to minimize the residual echo signal and achieve a higher data rate. The entire FDT architecture has been designed in TSMC 28 nm CMOS standard process with 0.9 V supply voltage. The performance results validate a 16 Gbps FD operation with a root-mean-square (RMS) jitter of 16.4 ps, and a power efficiency of 0.16 pJ/b/mm over a 5 mm on-chip interconnect without significant effect due to process-voltage-temperature (PVT) variations. To the best knowledge of the authors, this work shows the highest achievable full-duplex data rate, among the solutions reported in the literature to date, yet with low complexity, low layout area of 1581 μ m 2 and competitive power efficiency.

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