LP-HS Logic Evaluation on TSMC 0.18μm CMOS Technology

2017 ◽  
Vol 26 (04) ◽  
pp. 1740024
Author(s):  
Aloke Saha ◽  
Sushil Kumar ◽  
Debajit Das ◽  
Mrinmoy Chakraborty
Keyword(s):  
Power Efficiency ◽  
High Speed ◽  
Building Blocks ◽  
Cmos Technology ◽  
Worst Case ◽  
Temperature Variations ◽  
Noise Margin ◽  
Reliability Issue ◽  
Logic Threshold ◽  
System Focus

Present paper analyses different aspects of “Low Power-High Speed” (LP-HS) logic in favour of present day ULSI system focus. At first, the speed-power efficiency of LP-HS logic is investigated by designing some basic digital building blocks like Buffer, OR, AND, XOR etc. Next, the Voltage Transfer Characteristics (VTC), Noise Margin (NM) and the temperature effect on logic threshold with respect to LP-HS Buffer circuit are examined. The robustness and reliability of LP-HS Logic has been measured in terms of corner analysis with TT (Typical), FF (Fastest) and SS (Slowest) PVT (Process Voltage Temperature) variations on LP-HS XOR circuit. The worst case delay and PDP variation is recorded. Finally the 8:1 Multiplexer is designed, optimized and evaluated based on LP-HS Logic. The evaluated results are compared with some recent competitive designs to benchmark. To resolve reliability issue the corner analysis with PVT variation has been performed on designed 8:1 Multiplexor circuit. All the simulations are done on TSMC 0.18μm CMOS technology using Tanner EDA V.13 at 25°C temperature with 1.8V supply rail.

scholarly journals Low power and high speed GDI based convolution using Vedic multiplier

2018 ◽  
Vol 7 (2.7) ◽  
pp. 733
Author(s):  
C Priyanka ◽  
N Manoj Kumar ◽  
L Sai Priya ◽  
B Vaishnavi ◽  
M Rama Krishna
Keyword(s):  
Low Power ◽  
Impulse Response ◽  
High Speed ◽  
Digital Signal ◽  
Building Blocks ◽  
Cmos Technology ◽  
Low Power Consumption ◽  
Basic Building Block ◽  
Extensive Area ◽  
Vedic Multiplier

Convolution is having extensive area of application in Digital Signal Processing. Convolution supports to evaluate the output of a system with arbitrary input, with information of impulse response of the system.  Linear systems features are totally stated by the systems impulse response, as ruled by the mathematics of convolution. Primary necessity of any application to work fast is that rise in the speed of their basic building block. Multiplier, adder is said to be the important building blocks in the process of convolution. As these blocks consumes plentiful time to obtain the response of the system.  Several methods are designed to progress the speed of the Multiplier and adder, among all GDI (Gate Diffusion Input) is under emphasis because of faster working and low power consumption. In this paper GDI based convolution is implemented using Vedic multiplier and adder in T-SPICE Software which increases the speed and consumes less power compared to CMOS technology. 

scholarly journals Optimum multiplexer design in quantum-dot cellular automata

2020 ◽  
Vol 17 (1) ◽  
pp. 148 ◽  
Author(s):  
Esam AlKaldy ◽  
Ali H Majeed ◽  
Mohd Shamian Zainal ◽  
Danial MD Nor
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Boolean Function ◽  
High Speed ◽  
Building Blocks ◽  
Cmos Technology ◽  
Quantum Dot Cellular Automata ◽  
Quantum Technology ◽  
Logical Functions ◽  
Novel Design

<p>Quantum-dot Cellular Automata (QCA) is one of the most important computing technologies for the future and will be the alternative candidate for current CMOS technology. QCA is attracting a lot of researchers due to many features such as high speed, small size, and low power consumption. QCA has two main building blocks (majority gate and inverter) used for design any Boolean function. QCA also has an inherent capability that used to design many important gates such as XOR and Multiplexer in optimal form without following any Boolean function. This paper presents a novel design 2:1 QCA-Multiplexer in two forms. The proposed design is very simple, highly efficient and can be used to produce many logical functions. The proposed design output comes from the inherent capabilities of quantum technology. New 4:1 QCA-Multiplexer has been built using the proposed structure. The output waveforms showed the wonderful performance of the proposed design in terms of the number of cells, area, and latency.</p>

A Novel Method to Control Leakage and Noise in Domino Circuit for Wide Fan-in OR Logic

2021 ◽  
pp. 2250055
Author(s):  
Ankur Kumar ◽  
R. K. Nagaria
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Noise Immunity ◽  
Cmos Technology ◽  
Threshold Current ◽  
Delay Condition ◽  
Noise Margin ◽  
Novel Method ◽  
Domino Circuits

This paper proposes a novel method to control leakage and noise in domino circuits for wide fan-in OR logic with low power consumption, low process variation, and higher noise margin under the similar delay condition. In the proposed method, output and dynamic nodes are isolated from the PDN (Pull-Down Network) to improve the noise immunity and reduce switching activity. Further, with the aid of a transistor in the stack, the sub-threshold current is reduced. Thus, the proposed domino is applicable for high-speed and low-power applications in deep sub-micro-range. Simulation results show that the proposed domino improves the noise immunity and figure of merit (FOM) by factors of 1.95 and 2.34, respectively, with respect to the conventional domino with a footer. Along with this improvement, 26% reduction is also observed in power consumption. The entire simulations for all the domino circuits are done at 45-nm CMOS technology by using SPECTRE simulator under the Cadence Virtuoso environment.

scholarly journals A 1.25–12.5 Gbps Adaptive CTLE with Asynchronous Statistic Eye-Opening Monitor

2018 ◽  
Vol 2018 ◽  
pp. 1-9 ◽  
Author(s):  
Chen Cai ◽  
Jian-zhong Zhao ◽  
Yu-mei Zhou
Keyword(s):  
Power Efficiency ◽  
High Speed ◽  
Adaptive Equalization ◽  
Cmos Process ◽  
Worst Case ◽  
Eye Diagram ◽  
Chip Area ◽  
Serial Interface ◽  
Linear Equalization ◽  
Eye Opening

The equalization of a large attenuation signal and multirate communication in high-speed serial interface is hard to balance. To overcome this difficulty, an adaptive equalization system with optimized eye-opening monitor is proposed. The designed eye-opening monitor is based on the asynchronous statistic eye diagram tracking algorithm, and the eye diagram is obtained by undersampling with the low-speed asynchronous clock. With the eye-opening monitor into the adaptive loop, an adaptive equalization system combined with continuous-time linear equalization (CTLE) is completed. And the inductor peaking technology is used to improve the capacity of compensation. With SMIC 28 nm CMOS process to achieve the overall design, the power consumption and core chip area are 12 mW @ 12.5 Gbps and 0.12 mm2, respectively. And postsimulation results show that it can offer compensation from 6 to 21 dB for 1.25–12.5 Gbps range of receiving data, which achieves a large range of data rate and channel loss, and its power efficiency is 0.046 pJ/bit/dB for the worst case, which is better than most previous works.

scholarly journals A Hidden DCT-Based Invisible Watermarking Method for Low-Cost Hardware Implementations

Electronics ◽  
2021 ◽  
Vol 10 (12) ◽  
pp. 1465
Author(s):  
Yuxuan Wang ◽  
Yuanyong Luo ◽  
Zhongfeng Wang ◽  
Hongbing Pan
Keyword(s):  
Resource Sharing ◽  
Power Efficiency ◽  
High Speed ◽  
Low Cost ◽  
Color Space ◽  
Computational Cost ◽  
Cmos Technology ◽  
Hardware Implementations ◽  
Invisible Watermarking ◽  
Speed Performance

This paper presents an invisible and robust watermarking method and its hardware implementation. The proposed architecture is based on the discrete cosine transform (DCT) algorithm. Novel techniques are applied as well to reduce the computational cost of DCT and color space conversion to achieve low-cost and high-speed performance. Besides, a watermark embedder and a blind extractor are implemented in the same circuit using a resource-sharing method. Our approach is compatible with various watermarking embedding ratios, such as 1/16 and 1/64, with a PSNR of over 45 and the NC value of 1. After Joint Photographic Experts Group (JPEG) compression with a quality factor (QF) of 50, our method can achieve an NC value of 0.99. Results from a design compiler (DC) with TSMC-90 nm CMOS technology show that our design can achieve the frequency of 2.32 GHz with the area consumption of 304,980.08 μm2 and power consumption of 508.1835 mW. For the FPGA implementation, our method achieved a frequency of 421.94 MHz. Compared with the state-of-the-art works, our design improved the frequency by 4.26 times, saved 90.2% on area and increased the power efficiency by more than 1000 fold.

scholarly journals DESIGN, IMPLEMENTATION AND ANALYSIS OF FLASH ADC ARCHITECTURE WITH DIFFERENTIAL AMPLIFIER AS COMPARATOR USING CUSTOM DESIGN APPROACH

2012 ◽  
pp. 51-56
Author(s):  
CHANNAKKA LAKKANNAVAR ◽  
SHRIKANTH K. SHIRAKOL ◽  
KALMESHWAR N. HOSUR
Keyword(s):  
Data Storage ◽  
High Speed ◽  
Digital Signal ◽  
Building Blocks ◽  
Input Voltage ◽  
Cmos Technology ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Flash Adc ◽  
Analog To Digital

Analog-to-Digital Converters (ADCs) are useful building blocks in many applications such as a data storage read channel and an optical receiver because they represent the interface between the real world analog signal and the digital signal processors. Many implementations have been reported in the literature in order to obtain high-speed analog-todigital converters (ADCs). In this paper an effort is made to design 4-bit Flash Analog to Digital Converter [ADC] using 180nm cmos technology. For high-speed applications, a flash ADC is often used. Resolution, speed, and power consumption are the three key parameters for an Analog-to-Digital Converter (ADC). The integrated flash ADC is operated at 4-bit precision with analog input voltage of 0 to 1.8V. The ADC has been designed, implemented & analysed in standard gpdk180nm technology library using Cadence tool.

scholarly journals Estimation of Write Noise Margin for 6t SRAM Cell in CMOS 45nm technology.

2021 ◽  
Vol 23 (05) ◽  
pp. 211-215
Author(s):  
Hima Bindu Katikala ◽  
◽  
G. Ramana Murthy ◽  
P. Raja Rajeswari ◽  
P. Sai Charan ◽  
...  
Keyword(s):  
High Speed ◽  
Random Access ◽  
Cmos Technology ◽  
Propagation Delay ◽  
Noise Margin ◽  
Sram Cell ◽  
Scaling Process ◽  
Memory Architectures ◽  
Margin Analysis ◽  
Static Noise

For high speed application the static random access memory is mostly demandable. Such kind of device should possess additive parameters that can withstand during transistor scaling process. Their exist static noise margin (SNM) which degrades the device performance of memory architectures, majorly observed at write and read operation create write noise margin (WNM) and read noise margin (RNM). In this paper we discuss about the basic design of 6 transistor SRAM (6T SRAM) using 180nm and 45nm CMOS technology in Cadence Virtuoso with write noise margin analysis. The propagation delay, power dissipation, WNM are measured for both the technologies and observed that WNM is relatively low in 45nm.

scholarly journals A Ku-Band RF Front-End Employing Broadband Impedance Matching with 3.5 dB NF and 21 dB Conversion Gain in 45-nm CMOS Technology

Electronics ◽  
2020 ◽  
Vol 9 (3) ◽  
pp. 539
Author(s):  
Hafiz Usman Mahmood ◽  
Dzuhri Radityo Utomo ◽  
Seok-Kyun Han ◽  
Jusung Kim ◽  
Sang-Gug Lee
Keyword(s):  
Power Efficiency ◽  
Impedance Matching ◽  
Building Blocks ◽  
Cmos Technology ◽  
Low Noise ◽  
Common Source ◽  
Conversion Gain ◽  
Chip Area ◽  
Front End ◽  
Input Matching

This paper presents a K u -band RF receiver front-end with broadband impedance matching and amplification. The major building blocks of the proposed receiver front-end include a wideband low-noise amplifier (LNA) employing a cascade of resistive feedback inverter (RFI) and transformer-loaded common source amplifier, a down-conversion mixer with push–pull transconductor and complementary LO switching stage, and an output buffer. Push–pull architecture is employed extensively to maximize the power efficiency, bandwidth, and linearity. The proposed two-stage LNA employs the stagger-tuned frequency response in order to extend the RF bandwidth coverage. The input impedance of RFI is carefully analyzed, and a wideband input matching circuit incorporating only a single inductor is presented along with useful equivalent impedance matching models and detailed design analysis. The prototype chip was fabricated in 45-nm CMOS technology and dissipates 78 mW from a 1.2-V supply while occupying chip area of 0.29 mm 2 . The proposed receiver front-end provides 21 dB conversion gain with 7 GHz IF bandwidth, 3.5 dB NF, −15.7 dBm IIP 3 while satisfying <−10 dB input matching over the whole input band.

scholarly journals A 16 Gbps, Full-Duplex Transceiver over Lossy On-Chip Interconnects in 28 nm CMOS Technology

Electronics ◽  
2020 ◽  
Vol 9 (5) ◽  
pp. 717
Author(s):  
Arash Ebrahimi Jarihani ◽  
Sahar Sarafi ◽  
Michael Koeberle ◽  
Johannes Sturm ◽  
Andrea M. Tonello
Keyword(s):  
Power Efficiency ◽  
High Speed ◽  
Supply Voltage ◽  
Impedance Matching ◽  
Low Complexity ◽  
Cmos Technology ◽  
Data Rate ◽  
Full Duplex ◽  
On Chip ◽  
28 Nm

A high-speed full-duplex transceiver (FDT) over lossy on-chip interconnects is presented. The FDT employs a hybrid circuit to separate the inbound and outbound signals from each other and also performs echo-cancellation with the help of the main and the auxiliary drivers. A hybrid MOS device is utilized for impedance matching and conversion of the received voltage signal into a current signal for amplification. Moreover, a compensation capacitance ( C c ) is used at the output of the main driver to minimize the residual echo signal and achieve a higher data rate. The entire FDT architecture has been designed in TSMC 28 nm CMOS standard process with 0.9 V supply voltage. The performance results validate a 16 Gbps FD operation with a root-mean-square (RMS) jitter of 16.4 ps, and a power efficiency of 0.16 pJ/b/mm over a 5 mm on-chip interconnect without significant effect due to process-voltage-temperature (PVT) variations. To the best knowledge of the authors, this work shows the highest achievable full-duplex data rate, among the solutions reported in the literature to date, yet with low complexity, low layout area of 1581 μ m 2 and competitive power efficiency.

scholarly journals Design and Implementation of Novel Efficient Full Adder/Subtractor Circuits Based on Quantum-Dot Cellular Automata Technology

2021 ◽  
Vol 11 (18) ◽  
pp. 8717
Author(s):  
Mohsen Vahabi ◽  
Pavel Lyakhov ◽  
Ali Newaz Bahar
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
High Speed ◽  
Single Layer ◽  
Building Blocks ◽  
Full Adder ◽  
Cmos Technology ◽  
Quantum Dot Cellular Automata ◽  
Potential Alternative ◽  
Nanoscale Level

One of the emerging technologies at the nanoscale level is the Quantum-Dot Cellular Automata (QCA) technology, which is a potential alternative to conventional CMOS technology due to its high speed, low power consumption, low latency, and possible implementation at the atomic and molecular levels. Adders are one of the most basic digital computing circuits and one of the main building blocks of VLSI systems, such as various microprocessors and processors. Many research studies have been focusing on computable digital computing circuits. The design of a Full Adder/Subtractor (FA/S), a composite and computing circuit, performing both the addition and the subtraction processes, is of particular importance. This paper implements three new Full Adder/Subtractor circuits with the lowest number of cells, lowest area, lowest latency, and a coplanar (single-layer) circuit design, as was shown by comparing the results obtained with those of the best previous works on this topic.

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