A Temperature-Stable Low-Power Wide-Range CMOS Voltage Controlled Oscillator Design for Biomedical Applications

2019 ◽  
Vol 29 (08) ◽  
pp. 2050128
Author(s):  
Zied Sakka ◽  
Nadia Gargouri ◽  
Mounir Samet
Keyword(s):  
Low Power ◽  
Biomedical Applications ◽  
Cmos Technology ◽  
Average Frequency ◽  
Absolute Temperature ◽  
Ring Oscillator ◽  
Frequency Variation ◽  
Control Voltage ◽  
Voltage Controlled Oscillator ◽  
Wide Range

This paper presents a low power temperature compensated CMOS ring oscillator for biomedical applications across a wide temperature range. The proposed circuit deploys an IPTAT (inversely proportional to absolute temperature) bias current by generating an adaptive control voltage in each stage of the oscillator to compensate the overall oscillator’s temperature coefficient (TC). Simulations using TSMC 0.18[Formula: see text][Formula: see text]m CMOS technology show that this configuration can achieve a frequency variation less than 0.25%, leading to an average frequency drift of 20.83[Formula: see text]ppm/∘C. Monte Carlo simulations have also been performed and demonstrate a 3[Formula: see text] deviation of about 2.15%. The power dissipated by the proposed circuit is only 8.48[Formula: see text]mW at 25∘C.

scholarly journals A Low-Power Opamp-Less Second-Order Delta-Sigma Modulator for Bioelectrical Signals in 0.18 µm CMOS

Sensors ◽  
2021 ◽  
Vol 21 (19) ◽  
pp. 6456
Author(s):  
Fernando Cardes ◽  
Nikhita Baladari ◽  
Jihyun Lee ◽  
Andreas Hierlemann
Keyword(s):  
Low Power ◽  
Low Frequency ◽  
Cmos Technology ◽  
Low Noise ◽  
Second Order ◽  
Frequency Noise ◽  
Voltage Controlled Oscillator ◽  
Noise Shaping ◽  
Delta Sigma Modulator ◽  
Delta Sigma

This article reports on a compact and low-power CMOS readout circuit for bioelectrical signals based on a second-order delta-sigma modulator. The converter uses a voltage-controlled, oscillator-based quantizer, achieving second-order noise shaping with a single opamp-less integrator and minimal analog circuitry. A prototype has been implemented using 0.18 μm CMOS technology and includes two different variants of the same modulator topology. The main modulator has been optimized for low-noise, neural-action-potential detection in the 300 Hz–6 kHz band, with an input-referred noise of 5.0 μVrms, and occupies an area of 0.0045 mm2. An alternative configuration features a larger input stage to reduce low-frequency noise, achieving 8.7 μVrms in the 1 Hz–10 kHz band, and occupies an area of 0.006 mm2. The modulator is powered at 1.8 V with an estimated power consumption of 3.5 μW.

A 2.3 mW Multi-Frequency Clock Generator with −137 dBc/Hz Phase Noise VCO in 180 nm Digital CMOS Technology

2019 ◽  
Vol 29 (08) ◽  
pp. 2050130 ◽  
Author(s):  
Jagdeep Kaur Sahani ◽  
Anil Singh ◽  
Alpana Agarwal
Keyword(s):  
Phase Noise ◽  
Supply Voltage ◽  
Dead Zone ◽  
Dynamic Logic ◽  
Cmos Technology ◽  
Control Voltage ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Cmos Inverter ◽  
Digital Cmos

A fast phase frequency detector (PFD) and low gain low phase noise voltage-controlled oscillator (VCO)-based phase-locked loop (PLL) design are presented in this paper. PLL works in the frequency range of 0.025–1.6[Formula: see text]GHz, targeting various SoC applications. The proposed PFD, designed using CMOS dynamic logic, is fast and improves the locking time, dead zone and blind zone in the PLL. The standard CMOS inverter gate-based pseudo differential VCO is used in the PLL. Also, CMOS inverter is used as variable capacitor to tune the frequency of VCO with control voltage. The proposed PLL is designed in a 180[Formula: see text]nm CMOS process with supply voltage of 1.8[Formula: see text]V. The phase noise of VCO is [Formula: see text][Formula: see text]dBc/Hz at an offset frequency of 100[Formula: see text]MHz. The reference clock of 25[Formula: see text]MHz synthesizes the output clock of 1.6[Formula: see text]GHz with rms jitter of 0.642[Formula: see text]ps.

A low temperature drift coefficient crystal-less frequency reference clock compensated by temperature sensor for microsystem

2018 ◽  
Vol 32 (12) ◽  
pp. 1850146 ◽  
Author(s):  
Zhiqiang Gao ◽  
Ruixuan Wu ◽  
Yuteng Wang ◽  
Yuan Gao ◽  
Xiaowei Liu ◽  
...  
Keyword(s):  
Temperature Sensor ◽  
Current Source ◽  
Ring Oscillator ◽  
Frequency Variation ◽  
Control Voltage ◽  
Crystal Oscillator ◽  
Temperature Drift ◽  
Frequency Reference ◽  
Quartz Oscillator ◽  
Reference Clock

Quartz oscillator has been widely used as reference clock source in the microsystems due to its good performance. But a good crystal oscillator costs too much and its bulky size is not desired. This paper aims at designing an alternative integrated oscillator to replace the external quartz oscillator. The proposed circuit used maneatis delay cell to construct a ring oscillator for its superior linear I–V characteristic. As for a frequency reference clock, its frequency stability over temperature is required at first. After detailed mathematical deducing and careful analysis, a formula is proposed to describe the relationship between desired control voltage and temperature by assuming the frequency as constant. This paper utilized bipolar transistor as the temperature sensor, combining it with CTAT current source and resistor to create a first-order temperature compensation control voltage. The chip with typical frequency of 10 MHz was fabricated in a 0.35 [Formula: see text]m CMOS technology and occupied 0.45 mm2. The measured results show that the frequency variation is ±0.2% for supply changes from 4.8 V to 5 V, and frequency variation is 48 ppm when the temperature change is from −40[Formula: see text]C to 85[Formula: see text]C, while the average current of the tested chip consumes 50 [Formula: see text]A from 5 V.

scholarly journals Design of a very low-power, low-cost 60 GHz receiver front-end implemented in 65 nm CMOS technology

2011 ◽  
Vol 3 (2) ◽  
pp. 131-138 ◽  
Author(s):  
Michael Kraemer ◽  
Daniela Dragomirescu ◽  
Robert Plana
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Noise Figure ◽  
Low Cost ◽  
Cmos Technology ◽  
Low Noise ◽  
Oxide Semiconductor ◽  
Voltage Controlled Oscillator ◽  
60 Ghz ◽  
Front End

The research on the design of receiver front-ends for very high data-rate communication in the 60 GHz band in nanoscale Complementary Metal Oxide Semiconductor (CMOS) technologies is going on for some time now. Although a multitude of 60 GHz front-ends have been published in recent years, they are not consequently optimized for low power consumption. Thus, these front-ends dissipate too much power for battery-powered applications like handheld devices, mobile phones, and wireless sensor networks. This article describes the design of a direct conversion receiver front-end that addresses the issue of power consumption, while at the same time permitting low cost (due to area minimization by the use of spiral inductors). It is implemented in a 65 nm CMOS technology. The realized front-end achieves a record power consumption of only 43 mW including low-noise amplifier (LNA), mixer, a voltage controlled oscillator (VCO), a local oscillator (LO) buffer, and a baseband buffer (without this latter buffer the power consumption is even lower, only 29 mW). Its pad-limited size is 0.55 × 1 mm2. At the same time, the front-end achieves state-of-the-art performance with respect to its other properties: Its maximum measured power conversion gain is 30 dB, the RF and IF bandwidths are 56.5–61.5 and 0–1.5 GHz, respectively, its measured minimum noise figure is 9.2 dB, and its measured IP−1 dB is −36 dBm.

Sign in / Sign up

Export Citation Format

Share Document