Noise-Coupled Time-Interleaved Delta–Sigma Modulator with Reduced Hardware Complexity

2020 ◽  
pp. 2150071
Author(s):  
Mahmud Abdoli ◽  
Esmaeil Najafi Aghdam
Keyword(s):  
High Speed ◽  
Sampling Rate ◽  
Hardware Complexity ◽  
Analog To Digital ◽  
Noise Transfer Function ◽  
Delta Sigma Modulator ◽  
Novel Structure ◽  
Delta Sigma ◽  
Time Interleaved ◽  
Better Than

Developing an analog-to-digital converter (ADC) based on the time-interleaved delta–sigma modulator (TIDSM) is an appropriate technique to attain high-speed ADCs. TIDSMs can be successfully accomplished with the aid of developing the block digital filtering (BDF) method. In this approach, [Formula: see text] mutually cross-connection delta–sigma modulators are used, whereby each one of them operates at a sampling rate of [Formula: see text], leading to an effective sampling rate of [Formula: see text]. In this study, a novel structure is proposed based on the Noise Coupled time-interleaved delta–sigma modulator (NC-TIDSM) with reduced hardware complexity. This structure not only increases the overall noise transfer function (NTF) order, but also reduces the hardware element counts. The simulation results demonstrate that the SNDRs of the first-order two-channel and four-channel NC-TIDSM with reduced hardware are 13 and 15 dB better than those of their BDF technique counterparts; also, the SNDR of the second-order two-channel NC-TIDSM with reduced hardware is 8 dB better than that of their BDF technique counterpart; also, the hardware element quantities are reduced dramatically. Moreover, some practical challenges such as the finite op-amp’s gain and mismatching effects that directly affect the circuit implementation of the proposed structure have been described. Furthermore, the hardware complexity of the proposed structures is reduced considerably in comparison to that of the BDF technique with the NC-TIDSM structure.

An Encoder Used in an Ultra High-Speed Folding and Interpolating ADC

2014 ◽  
Vol 1049-1050 ◽  
pp. 687-690
Author(s):  
Yu Han Gao ◽  
Ru Zhang Li ◽  
Dong Bing Fu ◽  
Yong Lu Wang ◽  
Zheng Ping Zhang
Keyword(s):  
High Speed ◽  
Binary Code ◽  
Sampling Rate ◽  
Gray Code ◽  
Cmos Technology ◽  
Careful Consideration ◽  
Analog To Digital ◽  
Interleaved Adc ◽  
Time Interleaved ◽  
Error Suppression

High speed encoder is the key element of high speed analog-to-digital converter (ADC). Therefor the type of encoder, the type of code, bubble error suppression and bit synchronization must be taken into careful consideration especially for folding and interpolating ADC. To reduce the bubble error which may resulted from the circuit niose, comparator metastability and other interference, the output of quantizer is first encoded with gray code and then converted to binary code. This high speed encoder is verified in the whole time-interleaved ADC with 0.18 Bi-CMOS technology, the whole ADC can achieve a SNR of 45 dB at the sampling rate of 5GHz and input frequency of 495MHz, meanwhile a bit error rate (BER) of less than 10-16 is ensured by this design.

scholarly journals Delta-Sigma Modulator with Relaxed Feedback Timing for High Speed Applications

Electronics ◽  
2019 ◽  
Vol 8 (10) ◽  
pp. 1138
Author(s):  
Youngho Jung ◽  
Jooyoung Jeon
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Cmos Process ◽  
Dynamic Element Matching ◽  
Analog To Digital ◽  
Feedback Timing ◽  
Delta Sigma Modulator ◽  
Delta Sigma ◽  
Circuit Technique ◽  
Signal Band

In this paper, a ΔΣ analog-to-digital converter (ADC) was designed and measured for broadband and high-resolution applications by applying the simple circuit technique to alleviate the feedback timing of input feed-forward architecture. With the proposed technique, a low-speed comparator and dynamic element matching (DEM) logic can be applied even for high-speed implementation, which helps to decrease power dissipation. Two prototypes using slightly different input branch topologies were fabricated with a 0.18 um 2-poly and 4-metal CMOS process, and measured to demonstrate the effectiveness of the proposed circuit technique. The sampling capacitor and feedback DAC capacitors were separated in prototype A, while they were shared in prototype B. The prototypes achieved 81.2 dB and 72.4 dB of SNDR in a 2.1 MHz signal band, respectively.

NEW SAMPLING METHOD TO IMPROVE THE SFDR OF WIDE BANDWIDTH ADC DEDICATED TO NEXT GENERATION WIRELESS TRANSCEIVER

2004 ◽  
Vol 13 (06) ◽  
pp. 1183-1201
Author(s):  
KAMAL EL-SANKARY ◽  
ALI ASSI ◽  
MOHAMAD SAWAN
Keyword(s):  
High Speed ◽  
Sampling Method ◽  
Dynamic Range ◽  
Sampling Rate ◽  
Analog To Digital ◽  
Wireless Transceiver ◽  
Spurious Free Dynamic Range ◽  
Interleaved Adc ◽  
Time Interleaved ◽  
Free Dynamic

Modern wireless communication standards that support high rates of voice and video streaming need high-speed Analog-to-Digital Converters (ADCs) with wide Spurious-Free Dynamic Range (SFDR). Conventional time-interleaved ADCs suffer from spurious components that seriously affect the SFDR. In this paper, we present the mathematical background describing the effect of randomizing the samples among the interleaved ADCs and we propose a digitally oriented method based on this analysis to randomize the mismatches among the ADC channels. Analyses and simulations show the effectiveness of the proposed approach in multi-channel ADCs with arbitrary bit resolution, channel's number and sampling rate. For a 10-bit 500 MS/s ADC, the SFDR achieved using the proposed randomizing method can be as wide as 75 dB, which is an enhancement of more than 26 dB comparing to the conventional time interleaved ADC.

A High-Resolution and Low Offset Delta-Sigma Analog to Digital Converter for Detecting Photoplethysmography Signal

2021 ◽  
Author(s):  
Eka Fitrah Pribadi ◽  
Rajeev Kumar Pandey ◽  
Paul C.-P. Chao
Keyword(s):  
High Resolution ◽  
Continuous Time ◽  
Operational Amplifier ◽  
High Frequency ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Analog To Digital ◽  
Delta Sigma Modulator ◽  
Delta Sigma ◽  
Low Offset

Abstract A high-resolution, low offset delta-sigma analog to digital converter for detecting photoplethysmography (PPG) signal is presented in this study. The PPG signal is a bio-optical signal incorporated with heart functionality and located in the range of 0.1–10 Hz. The location to get PPG signal is on a pulsating artery. Thus the delta-sigma analog-to-digital (DS ADC) converter is designed specifically in that range. However, the DS ADC circuitry suffers from 1/f noise under 10 Hz frequency range. A chopper based operational amplifier is implemented in DS ADC to push the 1/f noise into high-frequency noise. The dc offset of the operational amplifier is also pushed to the high-frequency region. The DS ADC circuitry consists of a second-order continuous-time delta-sigma modulator. The delta-sigma modulator circuitry is designed and simulated using TSMC 180 nm technology. The continuous-time delta-sigma modulator active area layout is 746μm × 399 μm and fabricated using TSMC 180 nm technology. It operates in 100 Hz bandwidth and 4096 over-sampling ratios. The SFDR of the circuit is above 70 dB. The power consumption of the delta-sigma modulator is 35.61μW. The simulation is performed in three different kinds of corner, SS, TT, and FF corner, to guarantee the circuitry works in different conditions.

scholarly journals A Statistic-Based Calibration Method for TIADC System

2015 ◽  
Vol 2015 ◽  
pp. 1-9 ◽  
Author(s):  
Kuojun Yang ◽  
Shulin Tian ◽  
Peng Ye ◽  
Peng Zhang ◽  
Yuanjin Zheng
Keyword(s):  
Sampling Rate ◽  
Calibration Method ◽  
Wide Frequency Range ◽  
Accurate Estimation ◽  
Analog To Digital ◽  
Average Value ◽  
Gain Error ◽  
Sampling Points ◽  
Interleaved Adc ◽  
Time Interleaved

Time-interleaved technique is widely used to increase the sampling rate of analog-to-digital converter (ADC). However, the channel mismatches degrade the performance of time-interleaved ADC (TIADC). Therefore, a statistic-based calibration method for TIADC is proposed in this paper. The average value of sampling points is utilized to calculate offset error, and the summation of sampling points is used to calculate gain error. After offset and gain error are obtained, they are calibrated by offset and gain adjustment elements in ADC. Timing skew is calibrated by an iterative method. The product of sampling points of two adjacent subchannels is used as a metric for calibration. The proposed method is employed to calibrate mismatches in a four-channel 5 GS/s TIADC system. Simulation results show that the proposed method can estimate mismatches accurately in a wide frequency range. It is also proved that an accurate estimation can be obtained even if the signal noise ratio (SNR) of input signal is 20 dB. Furthermore, the results obtained from a real four-channel 5 GS/s TIADC system demonstrate the effectiveness of the proposed method. We can see that the spectra spurs due to mismatches have been effectively eliminated after calibration.

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