MAGNETIC LOGIC DEVICES FOR FUTURE COMPUTING SYSTEMS

SPIN ◽  
2013 ◽  
Vol 03 (04) ◽  
pp. 1340012 ◽  
Author(s):  
HAO MENG ◽  
GUCHANG HAN
Keyword(s):  
High Performance ◽  
Magnetic Domain ◽  
Complementary Metal Oxide Semiconductor ◽  
Computing System ◽  
Oxide Semiconductor ◽  
Logic Device ◽  
Computing Systems ◽  
Logic Devices ◽  
High Performance Computing System ◽  
Recent Developments

High performance computing system design based on complementary metal oxide semiconductor (CMOS) is facing more and more challenges due to the volatility, increased leak current and interconnection delay. Computations utilizing magnetic logic devices have attracted considerable interest as the potential alternatives because of their features of nonvolatility, re-configurability, unlimited endurance and low power consumption. Instead of using electron charges, the magnetic logic device stores and processes the data information by controlling spins, i.e., the magnetization states in a device. The emerging technologies related to the magnetic logic are mainly composed of three design schemes, i.e., the magnetoresistive logic, the magnetic quantum cellular automata and the magnetic domain wall logic. This paper will illustrate the principles as well as review the recent developments of these magnetic logic devices. Challenges and prospects of the future development are also discussed.

scholarly journals Creating of an individual modeling environment in a hybrid high-performance computing system

2020 ◽  
Vol 22 (3) ◽  
pp. 197-201
Author(s):  
K. I. Volovich ◽  
S. A. Denisov ◽  
S. I. Malkovsky
Keyword(s):  
High Performance Computing ◽  
High Performance ◽  
Optimal Solution ◽  
Computing System ◽  
Computing Environment ◽  
Computing Systems ◽  
Modeling Environment ◽  
Modeling Systems ◽  
High Performance Computing System ◽  
Performance Computing

The article is devoted to the problem of solving scientific problems in the field of high-performance computing systems. An approach to solving a certain kind of problems in materials science is the use of mathematical modeling technologies implemented by specialized modeling systems. The greatest efficiency of the modeling system is shown when deployed in hybrid high-performance computing systems (HHPC), which have high performance and allow solving problems in an acceptable time with sufficient accuracy. However, there are a number of limitations that affect the work of the research team with modeling systems in the HHPC computing environment: the need to access graphics accelerators at the stage of development and debugging of algorithms in the modeling system, the need to use several modeling systems in order to obtain the most optimal solution, the need to dynamically change settings modeling systems for solving problems. The solution to the problem of the above limitations is assigned to an individual modeling environment functioning in the HHPC computing environment. The optimal solution for creating an individual modeling environment is the technology of virtual containerization. An algorithm for the formation of an individual modeling environment in a hybrid high-performance computing complex based on the «docker» virtual containerization system is proposed. An individual modeling environment is created by installing the necessary software in the base container, setting environment variables, installing custom software and licenses. A feature of the algorithm is the ability to form a library image from a base container with a customized individual modeling environment. In conclusion, the direction for further research work is indicated. The algorithm presented in the article is independent of the implementation of the job management system and can be used for any high-performance computing system.

scholarly journals Implement of a high-performance computing system for parallel processing of scientific applications and the teaching of multicore and parallel programming

2018 ◽  
Author(s):  
Apolinar Velarde Martinez
Keyword(s):  
High Performance Computing ◽  
High Speed ◽  
High Performance ◽  
Education Institution ◽  
Computing System ◽  
Memory Systems ◽  
Distributed Computing Systems ◽  
Computing Systems ◽  
High Performance Computing System ◽  
Performance Computing

Increasingly complex algorithms for the modeling and resolution of different problems, which are currently facing humanity, has made it necessary the advent of new data processing requirements and the consequent implementation of high performance computing systems; but due to the high economic cost of this type of equipment and considering that an education institution cannot acquire, it is necessary to develop and implement computable architectures that are economical and scalable in their construction, such as heterogeneous distributed computing systems, constituted by several clustering of multicore processing elements with shared and distributed memory systems. This paper presents the analysis, design and implementation of a high-performance computing system called Liebres InTELigentes, whose purpose is the design and execution of intrinsically parallel algorithms, which require high amounts of storage and excessive processing times. The proposed computer system is constituted by conventional computing equipment (desktop computers, lap top equipment and servers), linked by a high-speed network. The main objective of this research is to build technology for the purposes of scientific and educational research.

Analysis and Evaluation of a New Algorithm Based Fault Tolerance for Computing Systems

2012 ◽  
Vol 4 (1) ◽  
pp. 37-51 ◽  
Author(s):  
Hodjat Hamidi ◽  
Abbas Vafaei ◽  
Seyed Amir Hassan Monadjemi
Keyword(s):  
Fault Tolerance ◽  
High Performance ◽  
Fault Tolerant ◽  
Numerical Algorithms ◽  
Computing System ◽  
Computing Systems ◽  
Specific Level ◽  
New Approach ◽  
Computing Paradigm ◽  
High Performance Computing System

In this paper, the authors present a new approach to algorithm based fault tolerance (ABFT) for High Performance computing system. The Algorithm Based Fault Tolerance approach transforms a system that does not tolerate a specific type of fault, called the fault-intolerant system, to a system that provides a specific level of fault tolerance, namely recovery. The ABFT techniques that detect errors rely on the comparison of parity values computed in two ways, the parallel processing of input parity values produce output parity values comparable with parity values regenerated from the original processed outputs, can apply convolution codes for the redundancy. This method is a new approach to concurrent error correction in fault-tolerant computing systems. This paper proposes a novel computing paradigm to provide fault tolerance for numerical algorithms. The authors also present, implement, and evaluate early detection in ABFT.

scholarly journals Ab initio perspective of ultra-scaled CMOS from 2D-material fundamentals to dynamically doped transistors

2021 ◽  
Vol 5 (1) ◽  
Author(s):  
Aryan Afzalian
Keyword(s):  
Field Effect ◽  
High Performance ◽  
Field Effect Transistor ◽  
High Mobility ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Grand Challenge ◽  
Gate Length ◽  
Delay Performance ◽  
Effect Transistor

AbstractUsing accurate dissipative DFT-NEGF atomistic-simulation techniques within the Wannier-Function formalism, we give a fresh look at the possibility of sub-10-nm scaling for high-performance complementary metal oxide semiconductor (CMOS) applications. We show that a combination of good electrostatic control together with high mobility is paramount to meet the stringent roadmap targets. Such requirements typically play against each other at sub-10-nm gate length for MOS transistors made of conventional semiconductor materials like Si, Ge, or III–V and dimensional scaling is expected to end ~12 nm gate-length (pitch of 40 nm). We demonstrate that using alternative 2D channel materials, such as the less-explored HfS2 or ZrS2, high-drive current down to ~6 nm is, however, achievable. We also propose a dynamically doped field-effect transistor concept, that scales better than its MOSFET counterpart. Used in combination with a high-mobility material such as HfS2, it allows for keeping the stringent high-performance CMOS on current and competitive energy-delay performance, when scaling down to virtually 0 nm gate length using a single-gate architecture and an ultra-compact design (pitch of 22 nm). The dynamically doped field-effect transistor further addresses the grand-challenge of doping in ultra-scaled devices and 2D materials in particular.

A High-Performance Computing System for Probabilistic Weather Forecasts

2019 ◽  
Author(s):  
Weiming Hu ◽  
Guido Cervone ◽  
Vivek Balasubramanian ◽  
Matteo Turilli ◽  
Shantenu Jha
Keyword(s):  
High Performance Computing ◽  
High Performance ◽  
Computing System ◽  
Weather Forecasts ◽  
High Performance Computing System ◽  
Performance Computing

Characterization of High-Performance Polycrystalline Silicon Complementary Metal–Oxide–Semiconductor Circuits

2007 ◽  
Vol 46 (1) ◽  
pp. 51-55 ◽  
Author(s):  
Genshiro Kawachi ◽  
Yoshiaki Nakazaki ◽  
Hiroyuki Ogawa ◽  
Masayuki Jyumonji ◽  
Noritaka Akita ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Polycrystalline Silicon ◽  
High Performance ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Semiconductor Circuits

scholarly journals A Multiplexed Chemical Sensing CMOS Imager

2021 ◽  
Author(s):  
Di Wang ◽  
Fenni Zhang ◽  
Kyle Mallires ◽  
Vishal Tipparaju ◽  
Jingjing Yu ◽  
...  
Keyword(s):  
Chemical Sensing ◽  
High Performance ◽  
Health Management ◽  
Complementary Metal Oxide Semiconductor ◽  
Spot Size ◽  
Oxide Semiconductor ◽  
Colorimetric Sensing ◽  
Widespread Application ◽  
Cmos Imager ◽  
Cmos Chip

Abstract A miniaturized and multiplexed chemical sensing technology is urgently needed to empower mobile devices, Internet-of-Things (IoTs) and robots for various new applications. Here, we show that a complementary metal-oxide-semiconductor (CMOS) imager can be turned into a multiplexed colorimetric sensing chip by coating micron-scale colorimetric sensing spots on the imager surface. Each sensing spot contains chemical sensing materials and nanoparticles for colorimetric signal enhancement. The sensitivity is spot-size invariant, and high-performance chemical sensing can be achieved on sensing spot as small as ~ 10 µm. This great scalability combined with millions of pixels of a CMOS imager offers a promising platform for highly integrated chemical sensors. Moreover, the chemical CMOS chip can be readily integrated with mobile electronics. As a proof-of-concept, we have built a smartphone accessary based on this chemical CMOS chip for personal health management. We anticipate that this new platform will pave the way for the widespread application of chemical sensing, such as mobile health (mHealth), IoTs, electronic nose, and smart homes.

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