Zero Additional Process, Local Charge Trap, Embedded Flash Memory with Drain-Side Assisted Erase Scheme Using Minimum Channel Length/Width Standard Complemental Metal–Oxide–Semiconductor Single Transistor Cell

2012 ◽  
Vol 51 ◽  
pp. 04DD02 ◽  
Author(s):  
Kousuke Miyaji ◽  
Yasuhiro Shinozuka ◽  
Ken Takeuchi
Keyword(s):  
Metal Oxide ◽  
Flash Memory ◽  
Channel Length ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Local Charge ◽  
Drain Side ◽  
Length Width ◽  
Additional Process ◽  
Embedded Flash

A metal‐oxide‐semiconductor field‐effect transistor with a 20‐nm channel length

1990 ◽  
Vol 68 (5) ◽  
pp. 2493-2495 ◽  
Author(s):  
A. Hartstein ◽  
N. F. Albert ◽  
A. A. Bright ◽  
S. B. Kaplan ◽  
B. Robinson ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Channel Length ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Effect Transistor ◽  
20 Nm

Impacts of ESD Reliability by Different Layout Engineering in the 0.25-μm 60-V High-Voltage LDMOS Devices

2018 ◽  
Vol 3 (2) ◽  
Author(s):  
Shen-Li Chen ◽  
Chun-Ju Lin ◽  
Huang Yu-Ting
Keyword(s):  
Metal Oxide ◽  
High Voltage ◽  
Electrostatic Discharge ◽  
Complementary Metal Oxide Semiconductor ◽  
Narrow Channel ◽  
Metal Oxide Semiconductor ◽  
Channel Width ◽  
Oxide Semiconductor ◽  
Drain Side ◽  
Better Than

Abstract How to effectively enhance the reliability robustness in high-voltage (HV) BCD [(bipolar) complementary metal-oxide semiconductor (CMOS) diffusion metaloxide semiconductor (DMOS)] processes is an important issue. Influences of layouttype dependences on anti-electrostatic discharge (ESD) robustness in a 0.25-μm 60-V process will be studied in this chapter, which includes, in part (1), the traditional striped-type n-channel lateral-diffused MOSFET (nLDMOS), waffle-type nLDMOS, and nLDMOS embedded with a “p-n-p”-arranged silicon-controlled rectifier (SCR) devices in the drain side; and in part (2) a p-channel LDMOS (pLDMOS) with an embedded “p-n-p-n-p”-arranged-type SCR in the drain side (diffusion regions of the drain side is P+-N+-P+-N+-P+). Then, these LDMOS devices are used to evaluate the influence of layout architecture on trigger voltage (Vt1), holding voltage (Vh), and secondary breakdown current (It2). Eventually, the sketching of the layout pattern of a HV LDMOS is a very important issue in the anti-ESD consideration. Also, in part (1), the waffle-type nLDMOS DUT contributes poorly to It2 robustness due to the non-uniform turned-on phenomenon and a narrow channel width per unit finger. Therefore, the It2 robustness of a waffle-type nLDMOS device is decreased about 17% as compared to a traditional striped-type nLDMOS device (reference DUT-1). The ESD abilities of traditional stripedtype and waffle-type nLDMOS devices with an embedded SCR (“p-n-p”-manner arrangement in the drain side) are better than a traditional nLDMOS 224.4% in average. Noteworthy, the nLDMOS-SCR with the “p-n-p” -arranged-type in the drainend is a good structure for the anti-ESD reliability especially in HV usages. Furthermore, in part (2) this layout manner of P+ discrete-island distributions in the drain-side have some impacts on the anti-ESD and anti-latch-up (LU) immunities. All of their It2 values have reached above 6 A; however, the major repercussion is that the Vh value will be decreased about 66.7 ~ 73.7%.

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