On-Chip Electrical Breakdown of Metallic Nanotubes for Mass Fabrication of Carbon-Nanotube-Based Electronic Devices

2008 ◽  
Vol 7 (5) ◽  
pp. 624-627 ◽  
Author(s):  
Gyoung-Ho Buh ◽  
Jea-Ho Hwang ◽  
Eun-Kyoung Jeon ◽  
Hye-Mi So ◽  
Jeong-O Lee ◽  
...  
2002 ◽  
Vol 80 (20) ◽  
pp. 3820-3822 ◽  
Author(s):  
C. Bower ◽  
W. Zhu ◽  
D. Shalom ◽  
D. Lopez ◽  
L. H. Chen ◽  
...  

2021 ◽  
Author(s):  
Femi Robert

Abstract This paper exhibits the electrothermal modelling and evaluation of Carbon Nanotube (CNT) based electrical interconnects for electronic devices. The continuum model of the CNT is considered and the temperature across interconnect is predicted for the given power. Finite element modelling software COMSOL Multiphysics is used to carry out the simulations. The results are compared with Al and Cu interconnects. An electrothermal analysis is also carried out to obtain the temperature for the given power for Single-Walled CNT, Double-Walled CNT, Triple-Walled CNT, and Multi-Walled CNT. Results show that the CNT interconnects performs better when compared to Al and Cu interconnects. The power withstanding capability of CNT is 68.75 times more than Al and 32.35 times more than Cu. Based on the transient analysis, the time taken by the CNT interconnects to reach a steady temperature is obtained as 0.007 ns. On the application of power, Cu and Al interconnects takes 0.1 ns to reach the steady-state temperature. The nanostructured CNT based electrical interconnects would play a considerable role in replacing Cu and Al electrical interconnect applications for micro and nanoelectronic devices.


2022 ◽  
Vol 17 (1) ◽  
Author(s):  
Xian Shi ◽  
Xiaoqiao He ◽  
Ligang Sun ◽  
Xuefeng Liu

Abstract Networks based on carbon nanotube (CNT) have been widely utilized to fabricate flexible electronic devices, but defects inevitably exist in these structures. In this study, we investigate the influence of the CNT-unit defects on the mechanical properties of a honeycomb CNT-based network, super carbon nanotube (SCNT), through molecular dynamics simulations. Results show that tensile strengths of the defective SCNTs are affected by the defect number, distribution continuity and orientation. Single-defect brings 0 ~ 25% reduction of the tensile strength with the dependency on defect position and the reduction is over 50% when the defect number increases to three. The distribution continuity induces up to 20% differences of tensile strengths for SCNTs with the same defect number. A smaller arranging angle of defects to the tensile direction leads to a higher tensile strength. Defective SCNTs possess various modes of stress concentration with different concentration degrees under the combined effect of defect number, arranging direction and continuity, for which the underlying mechanism can be explained by the effective crack length of the fracture mechanics. Fundamentally, the force transmission mode of the SCNT controls the influence of defects and the cases that breaking more force transmission paths cause larger decreases of tensile strengths. Defects are non-negligible factors of the mechanical properties of CNT-based networks and understanding the influence of defects on CNT-based networks is valuable to achieve the proper design of CNT-based electronic devices with better performances. Graphical Abstract


2021 ◽  
Vol 8 ◽  
Author(s):  
Zhenzhong Hou ◽  
Hai Lu ◽  
Ying Li ◽  
Laixia Yang ◽  
Yang Gao

Recently, the fabrication of electronics-related components via direct ink writing (DIW) has attracted much attention. Compared to the conventionally fabricated electronic components, DIW-printed ones have more complicated structures, higher accuracy, improved efficiency, and even enhanced performances that arise from well-designed architectures. The DIW technology allows directly print materials on a variety of flat substrates, even a conformal one, well suiting them to applications such as wearable devices and on-chip integrations. Here, recent developments in DIW printing of emerging components for electronics-related applications are briefly reviewed, including electrodes, electronic circuits, and functional components. The printing techniques, processes, ink materials, advantages, and properties of DIW-printed architectures are discussed. Finally, the challenges and outlooks on the manufacture of 3D structured electronic devices by DIW are outlined, pointing out future designs and developments of DIW technology for electronics-related applications. The combination of DIW and electronic devices will help to improve the quality of human life and promote the development of science and society.


2006 ◽  
Vol 963 ◽  
Author(s):  
Jun Huang ◽  
Bangalore Kiran Rao ◽  
Harindra Vedala ◽  
Do-Hyun Kim ◽  
Minhyon Jeon ◽  
...  

ABSTRACTGeometrically controlled single-walled carbon nanotube (SWNT) and multi-walled carbon nanotube (MWNT) networks were fabricated by a width confinement technique to characterize their electrical characteristics. The results demonstrated non-linear resistance decay with the number of conducting channels. The current-voltage characteristics at high field were studied until the electrical breakdown took place. Large current (∼2 mA), low resistance (∼5 KΩ) and current densities exceeding ∼108 A/cm2 were demonstrated from multi-channel MWNT networks confined in a 10 μm × 15 μm trench. Additionally, chronological SEM imaging was used to identify the breakdown sequences in the carbon nanotube networks, which revealed a strong tendency for CNT breakdown to occur in the vicinity of CNT-CNT intersections. Our results offer insights for interconnect applications using CNT networks.


2020 ◽  
Vol 201 (5-6) ◽  
pp. 772-802 ◽  
Author(s):  
A. T. Jones ◽  
C. P. Scheller ◽  
J. R. Prance ◽  
Y. B. Kalyoncu ◽  
D. M. Zumbühl ◽  
...  

AbstractHere we review recent progress in cooling micro-/nanoelectronic devices significantly below 10 mK. A number of groups worldwide are working to produce sub-millikelvin on-chip electron temperatures, motivated by the possibility of observing new physical effects and improving the performance of quantum technologies, sensors and metrological standards. The challenge is a longstanding one, with the lowest reported on-chip electron temperature having remained around 4 mK for more than 15 years. This is despite the fact that microkelvin temperatures have been accessible in bulk materials since the mid-twentieth century. In this review, we describe progress made in the last 5 years using new cooling techniques. Developments have been driven by improvements in the understanding of nanoscale physics, material properties and heat flow in electronic devices at ultralow temperatures and have involved collaboration between universities and institutes, physicists and engineers. We hope that this review will serve as a summary of the current state of the art and provide a roadmap for future developments. We focus on techniques that have shown, in experiment, the potential to reach sub-millikelvin electron temperatures. In particular, we focus on on-chip demagnetisation refrigeration. Multiple groups have used this technique to reach temperatures around 1 mK, with a current lowest temperature below 0.5 mK.


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