Modeling of Thermo-Mechanical Stresses in Copper Interconnect/Low-k Dielectric Systems

2005 ◽  
Author(s):  
Y.-L. Shen
Keyword(s):  
Structural Integrity ◽  
Temperature Response ◽  
Future Generation ◽  
Interface Fracture ◽  
Deformation Pattern ◽  
Barrier Layers ◽  
Copper Interconnect ◽  
On Chip ◽  
Interconnect Systems ◽  
Low K

Systematic finite element analyses are carried out to model the thermomechanical stresses in on-chip copper interconnect systems. Constitutive behavior of encapsulated copper films, determined by experimentally measuring the stress-temperature response during thermal cycling, is used in the model for predicting stresses in copper interconnect/low-k dielectric structures. Various combinations of oxide and polymer-based low-k dielectric schemes are considered. The evolution of stresses and deformation pattern in the dual-damascene copper, barrier layers, and the dielectrics is seen to have direct connections to the structural integrity of contemporary and future-generation devices. In particular, stresses experienced by the thin barrier layers and the mechanically weak low-k dielectrics are critically assessed. A parametric analysis on the influence of low-k material properties is also conducted. Practical implications in reliability issues such as voiding, interface fracture, electromigration and dielectric failure are discussed.

Thermomechanical Stresses in Copper Interconnect/Low-κ Dielectric Systems

2004 ◽  
Vol 812 ◽  
Author(s):  
Y.-L. Shen ◽  
E. S. Ege
Keyword(s):  
Finite Element ◽  
Metal Oxide ◽  
Numerical Simulations ◽  
Thermal Stresses ◽  
Three Dimensional ◽  
Deformation Pattern ◽  
Barrier Layers ◽  
Copper Interconnect ◽  
Dimensional Finite Element ◽  
Three Dimensional Finite Element

AbstractNumerical simulations of thermal stresses in copper interconnect and low-κ dielectric systems are carried out. The analyses include two- and three-dimensional finite element modeling of the interconnect structure. Various combinations of metal, oxide and polymer-based low-κ dielectric schemes are considered in the simulation. The evolution of stresses and deformation pattern in copper, barrier layers, and the dielectrics are critically assessed.

Integration of Al-Fill Processes for Contacts and VIAS

1996 ◽  
Vol 427 ◽  
Author(s):  
H. J. Barth
Keyword(s):  
High Pressure ◽  
Chip Design ◽  
Size And Shape ◽  
Future Developments ◽  
Pattern Density ◽  
New Challenges ◽  
On Chip ◽  
Damascene Interconnects ◽  
Low K ◽  
Electrical Data

AbstractToday different Al-fill techniques are used for the fill of submicron contacts and vias. The integration aspects of the most promising approaches, Al-reflow, cold/hot Al-planarization and high pressure Al-fill (Forcefill) are compared to the widely used W-plug technique. The filling properties are discussed with respect to future applications in ULSI devices. Special attention is given to the barrier stability in contacts and the influence on patterning. Various electrical data and reliability results are compared to metallizations with W-plugs. The implications of the Al-fill processes on chip design, especially on the size and shape of holes, the pattern density, the possibility of producing stacked contacts/vias and the metal to contact/via overlap are considered also. In an outlook for future developments, e.g. the introduction of low k dielectrics, the inverse metallization architecture with (dual) damascene interconnects and the emerging Cu metallizations, Alfill processes are facing new challenges which will be discussed.

scholarly journals TRANSIENT RESPONSE OF A DISTRIBUTED RLC INTERCONNECT BASED ON DIRECT POLE EXTRACTION

2009 ◽  
Vol 18 (07) ◽  
pp. 1263-1285 ◽  
Author(s):  
GUOQING CHEN ◽  
EBY G. FRIEDMAN
Keyword(s):  
Closed Form ◽  
Transient Response ◽  
Transmission Lines ◽  
Average Error ◽  
Proposed Model ◽  
Newton Raphson ◽  
On Chip ◽  
Interconnect Systems ◽  
Interconnect System ◽  
Raphson Method

With higher operating frequencies, transmission lines are required to model global on-chip interconnects. In this paper, an accurate and efficient solution for the transient response at the far end of a transmission line based on a direct pole extraction of the system is proposed. Closed form expressions of the poles are developed for two special interconnect systems: an RC interconnect and an RLC interconnect with zero driver resistance. By performing a system conversion, the poles of an interconnect system with general circuit parameters are solved. The Newton–Raphson method is used to further improve the accuracy of the poles. Based on these poles, closed form expressions for the step and ramp response are determined. Higher accuracy can be obtained with additional pairs of poles. The computational complexity of the model is proportional to the number of pole pairs. With two pairs of poles, the average error of the 50% delay is 1% as compared with Spectre simulations. With ten pairs of poles, the average error of the 10%-to-90% rise time and the overshoots is 2% and 1.9%, respectively. Frequency dependent effects are also successfully included in the proposed method and excellent match is observed between the proposed model and Spectre simulations.

Mesoporous SiO2 as low-k dielectric for integration in Cu/low-k interconnect systems

2006 ◽  
Vol 18 (S1) ◽  
pp. 31-36
Author(s):  
Swantje Frühauf ◽  
Stefan E. Schulz ◽  
Thomas Gessner
Keyword(s):  
Mesoporous Sio2 ◽  
Interconnect Systems ◽  
Low K

Advanced 3D Packaging of Chips and Materials Integrity: Stress-Induced Effects and Mechanical Properties of New Ultra Low-k Dielectrics for On-Chip Interconnect Stacks

2013 ◽  
Vol 592-593 ◽  
pp. 563-568
Author(s):  
Christoph Sander ◽  
Martin Gall ◽  
Kong Boon Yeap ◽  
Ehrenfried Zschech
Keyword(s):  
Computing Time ◽  
Orientation Dependence ◽  
Chip Design ◽  
Simulation Methodology ◽  
3D Packaging ◽  
Internal Mechanical Stress ◽  
On Chip ◽  
Physics Based Simulation ◽  
Low K ◽  
Chip Analysis

Managing the emerging internal mechanical stress in chips particularly if they are 3D-tscked is a key task to maintain performance and reliability of microelectronic products. Hence, a strong need of a physics-based simulation methodology/flow emerges. This physics-based simulation, however, requires materials parameters with high accuracy. A full-chip analysis can then be performed, balancing the need for local resolution and computing time. Therefore, effective composite-type materials data for several regions of interest are needed. Advanced techniques to measure FEA-and design-relevant properties such as local and effective Youngs modulus and effective CTE values were developed and described in this paper. These data show a clear orientation dependence, caused by the chip design.

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