Voltage-Based Covert Channels Using FPGAs

2021 ◽  
Vol 26 (6) ◽  
pp. 1-25
Author(s):  
Dennis R. E. Gnad ◽  
Cong Dang Khoa Nguyen ◽  
Syed Hashim Gillani ◽  
Mehdi B. Tahoori
Keyword(s):  
Error Rate ◽  
Power Distribution ◽  
Covert Channel ◽  
Power Distribution Network ◽  
Synchronous Circuits ◽  
Logical Connection ◽  
Systems On Chip ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
On Chip

Field Programmable Gate Arrays ( FPGAs ) are increasingly used in cloud applications and being integrated into Systems-on-Chip. For these systems, various side-channel attacks on cryptographic implementations have been reported, motivating one to apply proper countermeasures. Beyond cryptographic implementations, maliciously introduced covert channel receivers and transmitters can allow one to exfiltrate other secret information from the FPGA. In this article, we present a fast covert channel on FPGAs, which exploits the on-chip power distribution network. This can be achieved without any logical connection between the transmitter and receiver blocks. Compared to a recently published covert channel with an estimated 4.8 Mbit/s transmission speed, we show 8 Mbit/s transmission and reduced errors from around 3% to less than 0.003%. Furthermore, we demonstrate proper transmissions of word-size messages and test the channel in the presence of noise generated from other residing tenants’ modules in the FPGA. When we place and operate other co-tenant modules that require 85% of the total FPGA area, the error rate increases to 0.02%, depending on the platform and setup. This error rate is still reasonably low for a covert channel. Overall, the transmitter and receiver work with less than 3–5% FPGA LUT resources together. We also show the feasibility of other types of covert channel transmitters, in the form of synchronous circuits within the FPGA.

scholarly journals Implementation of an ARM-based system using a Xilinx ZYNQ SoC

2019 ◽  
Vol 13 (2) ◽  
pp. 485
Author(s):  
Omar Salem Baans ◽  
Asral Bahari Jambek
Keyword(s):  
Embedded Systems ◽  
Field Programmable Gate Arrays ◽  
System On Chip ◽  
Software System ◽  
Gate Arrays ◽  
Arm Processor ◽  
Systems On Chip ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
On Chip

<span>ARM processors are widely used in embedded systems. They are often implemented as microcontrollers, field-programmable gate arrays (FPGAs) or systems-on-chip. In this paper, a variety of ARM processor platform implementations are reviewed, such as implementation into a microcontroller, a system-on-chip and a hybrid ARM-FPGA platform. Furthermore, the implementation of a specific ARM processor, the Cortex-A9 processor, into a system-on-chip (SoC) on an FPGA is discussed using Xilinx’s Vivado and SDK software system and execution on a Xilinx Zynq Board.</span>

Single Event Test Methodologies and System Error Rate Analysis for Triple Modular Redundant Field Programmable Gate Arrays

2011 ◽  
Vol 58 (3) ◽  
pp. 1040-1046 ◽  
Author(s):  
Gregory Allen ◽  
Larry D. Edmonds ◽  
Gary Swift ◽  
Carl Carmichael ◽  
Chen Wei Tseng ◽  
...  
Keyword(s):  
Error Rate ◽  
Field Programmable Gate Arrays ◽  
Single Event ◽  
System Error ◽  
Gate Arrays ◽  
Rate Analysis ◽  
Field Programmable ◽  
Programmable Gate Arrays

scholarly journals An Efficient FPGA-Based Convolutional Neural Network for Classification: Ad-MobileNet

Electronics ◽  
2021 ◽  
Vol 10 (18) ◽  
pp. 2272
Author(s):  
Safa Bouguezzi ◽  
Hana Ben Fredj ◽  
Tarek Belabed ◽  
Carlos Valderrama ◽  
Hassene Faiedh ◽  
...  
Keyword(s):  
Recognition Rate ◽  
Hardware Acceleration ◽  
Implementation Model ◽  
Gate Arrays ◽  
Proposed Model ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Computer Vision Applications ◽  
On Chip ◽  
Segmentation Image

Convolutional Neural Networks (CNN) continue to dominate research in the area of hardware acceleration using Field Programmable Gate Arrays (FPGA), proving its effectiveness in a variety of computer vision applications such as object segmentation, image classification, face detection, and traffic signs recognition, among others. However, there are numerous constraints for deploying CNNs on FPGA, including limited on-chip memory, CNN size, and configuration parameters. This paper introduces Ad-MobileNet, an advanced CNN model inspired by the baseline MobileNet model. The proposed model uses an Ad-depth engine, which is an improved version of the depth-wise separable convolution unit. Moreover, we propose an FPGA-based implementation model that supports the Mish, TanhExp, and ReLU activation functions. The experimental results using the CIFAR-10 dataset show that our Ad-MobileNet has a classification accuracy of 88.76% while requiring little computational hardware resources. Compared to state-of-the-art methods, our proposed method has a fairly high recognition rate while using fewer computational hardware resources. Indeed, the proposed model helps to reduce hardware resources by more than 41% compared to that of the baseline model.

Low-Complexity Nonlinear Self-Inverse Permutation for Creating Physically Clone-Resistant Identities

Cryptography ◽  
2020 ◽  
Vol 4 (1) ◽  
pp. 6 ◽  
Author(s):  
Saleh Mulhem ◽  
Ayoub Mars ◽  
Wael Adi
Keyword(s):  
Field Programmable Gate Arrays ◽  
Low Complexity ◽  
System On Chip ◽  
Large Classes ◽  
Physical Unclonable Functions ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Security Levels ◽  
On Chip

New large classes of permutations over ℤ 2 n based on T-Functions as Self-Inverting Permutation Functions (SIPFs) are presented. The presented classes exhibit negligible or low complexity when implemented in emerging FPGA technologies. The target use of such functions is in creating the so called Secret Unknown Ciphers (SUC) to serve as resilient Clone-Resistant structures in smart non-volatile Field Programmable Gate Arrays (FPGA) devices. SUCs concepts were proposed a decade ago as digital consistent alternatives to the conventional analog inconsistent Physical Unclonable Functions PUFs. The proposed permutation classes are designed and optimized particularly to use non-consumed Mathblock cores in programmable System-on-Chip (SoC) FPGA devices. Hardware and software complexities for realizing such structures are optimized and evaluated for a sample expected target FPGA technology. The attained security levels of the resulting SUCs are evaluated and shown to be scalable and usable even for post-quantum crypto systems.

Efficient Use of On-Chip Memories and Scheduling Techniques to Eliminate the Reconfiguration Overheads in Reconfigurable Systems

2019 ◽  
Vol 28 (14) ◽  
pp. 1950246
Author(s):  
I. Hariharan ◽  
M. Kannan
Keyword(s):  
System Performance ◽  
Replacement Policy ◽  
Reconfigurable Systems ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Configuration Data ◽  
On Chip ◽  
Time And Energy ◽  
Static Systems

Modern embedded systems are packed with dedicated Field Programmable Gate Arrays (FPGAs) to accelerate the overall system performance. However, the FPGAs are susceptible to reconfiguration overheads. The reconfiguration overheads are mainly because of the configuration data being fetched from the off-chip memory at run-time and also due to the improper management of tasks during execution. To reduce these overheads, our proposed methodology mainly focuses on the prefetch heuristic, reuse technique, and the available memory hierarchy to provide an efficient mapping of tasks over the available memories. Our paper includes a new replacement policy which reduces the overall time and energy reconfiguration overheads for static systems in their subsequent iterations. It is evident from the result that most of the reconfiguration overheads are eliminated when the applications are managed and executed based on our methodology.

scholarly journals New Mathblocks-Based Feistel-Like Ciphers for Creating Clone-Resistant FPGA Devices

Cryptography ◽  
2019 ◽  
Vol 3 (4) ◽  
pp. 28 ◽  
Author(s):  
Saleh Mulhem ◽  
Wael Adi
Keyword(s):  
Hard Core ◽  
Major Elements ◽  
Physical Unclonable Functions ◽  
Mapping Functions ◽  
The Public ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
On Chip ◽  
Near Future

The Secret Unknown Cipher (SUC) concept was introduced a decade ago as a promising technique for creating pure digital clone-resistant electronic units as alternatives to the traditional non-consistent Physical Unclonable Functions (PUFs). In this work, a very special unconventional cipher design is presented. The design uses hard-core FPGA (Field Programmable Gate Arrays) -Mathblocks available in modern system-on-chip (SoC) FPGAs. Such Mathblocks are often not completely used in many FPGA applications; therefore, it seems wise to make use of such dead (unused) modules to fabricate usable physical security functions for free. Standard cipher designs usually avoid deploying multipliers in the cipher mapping functions due to their high complexity. The main target of this work is to design large cipher classes (e.g., cipher class size >2600) by mainly deploying the FPGA specific mathematical cores. The proposed cipher designs are novel hardware-oriented and new in the public literature, using fully new unusual mapping functions. If a random unknown selection of one cipher out of 2600 ciphers is self-configured in a device, then a Secret Unknown Cipher module is created within a device, making it physically hard to clone. We consider the cipher module for free (for zero cost) if the major elements in the cipher module are making use of unused reanimated Mathblocks. Such ciphers are usable in many future mass products for protecting vehicular units against cloning and modeling attacks. The required self-reconfigurable devices for that concept are not available now; however, they are expected to emerge in the near future.

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