scholarly journals SecNVM: An Efficient and Write-Friendly Metadata Crash Consistency Scheme for Secure NVM

2022 ◽  
Vol 19 (1) ◽  
pp. 1-26
Author(s):  
Mengya Lei ◽  
Fan Li ◽  
Fang Wang ◽  
Dan Feng ◽  
Xiaomin Zou ◽  
...  
Keyword(s):  
Data Security ◽  
Recovery Time ◽  
State Of The Art ◽  
The State ◽  
Fast Recovery ◽  
Non Volatile Memory ◽  
User Data ◽  
Metadata Cache ◽  
Volatile Memory ◽  
The Cost

Data security is an indispensable part of non-volatile memory (NVM) systems. However, implementing data security efficiently on NVM is challenging, since we have to guarantee the consistency of user data and the related security metadata. Existing consistency schemes ignore the recoverability of the SGX style integrity tree (SIT) and the access correlation between metadata blocks, thereby generating unnecessary NVM write traffic. In this article, we propose SecNVM, an efficient and write-friendly metadata crash consistency scheme for secure NVM. SecNVM utilizes the observation that for a lazily updated SIT, the lost tree nodes after a crash can be recovered by the corresponding child nodes in NVM. It reduces the SIT persistency overhead through a restrained write-back metadata cache and exploits the SIT inter-layer dependency for recovery. Next, leveraging the strong access correlation between the counter and DMAC, SecNVM improves the efficiency of security metadata access through a novel collaborative counter-DMAC scheme. In addition, it adopts a lightweight address tracker to reduce the cost of address tracking for fast recovery. Experiments show that compared to the state-of-the-art schemes, SecNVM improves the performance and decreases write traffic a lot, and achieves an acceptable recovery time.

scholarly journals Solving Delete Free Planning with Relaxed Decision Diagram Based Heuristics

2020 ◽  
Vol 67 ◽  
pp. 607-651
Author(s):  
Margarita Paz Castro ◽  
Chiara Piacentini ◽  
Andre Augusto Cire ◽  
J. Christopher Beck
Keyword(s):  
Linear Programming ◽  
Empirical Analysis ◽  
State Of The Art ◽  
The State ◽  
Decision Diagrams ◽  
Binary Decision ◽  
Admissible Heuristics ◽  
The Cost ◽  
Construction Algorithms ◽  
Diagram Representation

We investigate the use of relaxed decision diagrams (DDs) for computing admissible heuristics for the cost-optimal delete-free planning (DFP) problem. Our main contributions are the introduction of two novel DD encodings for a DFP task: a multivalued decision diagram that includes the sequencing aspect of the problem and a binary decision diagram representation of its sequential relaxation. We present construction algorithms for each DD that leverage these different perspectives of the DFP task and provide theoretical and empirical analyses of the associated heuristics. We further show that relaxed DDs can be used beyond heuristic computation to extract delete-free plans, find action landmarks, and identify redundant actions. Our empirical analysis shows that while DD-based heuristics trail the state of the art, even small relaxed DDs are competitive with the linear programming heuristic for the DFP task, thus, revealing novel ways of designing admissible heuristics.

Non Volatile Memory Technologies: Floating Gate Concept Evolution

2004 ◽  
Vol 830 ◽  
Author(s):  
Cesare Clementi ◽  
Roberto Bez
Keyword(s):  
Data Storage ◽  
Flash Memory ◽  
Floating Gate ◽  
Nand Flash ◽  
Know How ◽  
Technology Node ◽  
Cell Architecture ◽  
Non Volatile Memory ◽  
Volatile Memory ◽  
The Cost

ABSTRACTThe most relevant phenomenon of this last decade in the field of semiconductor memories has been the explosive growth of the Flash memory market, driven by cellular phones and other types of electronic portable equipments (palm top, mobile PC, mp3 audio player, digital camera and so on). Moreover, in the coming years portable systems will ask even more non volatile memories either with high density and very high writing throughput for data storage application, or with fast random access for code execution in place. The strong consolidated know-how (more than ten years of experience), the flexibility and the cost make the floating gate Flash Memory a largely utilized, well-consolidated and mature technology for most of the non-volatile memory application. Today Flash sales represent a considerable amount of the overall semiconductor market.Nowadays two of the several cell architecture proposed up to now can be considered as industry standard: the common ground NOR Flash that due to its versatility is addressing both the code and data storage segments and the NAND Flash, optimized for the data storage market.The exploitation of the multilevel approach at each technology node allows the increase of the memory efficiency, about doubling the density at the same chip size, widening the application range and reducing the cost per bit.In this paper the main issues related to both NOR and NAND Flash memory technology will be summarized, with the aim of describing both the basic functionality of the memory cell and the main cell architecture today consolidated. Both cells are basically a floating-gate MOS transistor, programmed by channel hot electron (NOR) or by Fowler-Nordheim tunneling (NAND) and erased by Fowler-Nordheim tunnel. The main reliability properties, charge retention and endurance, are presented, together with some comments on the basic physical mechanisms responsible for.A couple of innovative approaches to floating gate cell evolution, namely nanocrystal memory and 3-D cell will be described.Finally the Flash cell scaling issues will be covered, pointing out the main challenges. The Flash cell scaling has been demonstrated to be really possible and to be able to follow the Moore's law down to the 90 nm technology generations. The technology development and the consolidated know-how are expected to sustain the scaling trend down to the 50 nm technology node and below as forecasted by the ITRS roadmap.

Advanced TEM Techniques for Mechanisms and Reliability Analysis in State-of-the-Art OxRAM and PCM Non-Volatile Memory Devices

2020 ◽  
Vol MA2020-02 (31) ◽  
pp. 2035-2035
Author(s):  
Gauthier Lefèvre ◽  
Nicolas Guillaume ◽  
Anna-Lisa Serra ◽  
Sylvain David ◽  
Christophe Vallée ◽  
...  
Keyword(s):  
Reliability Analysis ◽  
State Of The Art ◽  
Memory Devices ◽  
Non Volatile Memory ◽  
Volatile Memory

scholarly journals Evaluation of the Feasibility of Parametric Estimation in Devops Continuous Planning

2021 ◽  
Vol 9 (9) ◽  
pp. 542-546
Author(s):  
Dr. Diwakar Ramanuj Tripathi
Keyword(s):  
Development Process ◽  
State Of The Art ◽  
Value Added ◽  
The State ◽  
Parametric Estimation ◽  
Effort Estimation ◽  
Continuous Testing ◽  
Exploratory Testing ◽  
The Cost ◽  
Parametric Estimate

Abstract: DevOps aims to shorten project schedules, boost productivity, and manage quick development-deployment cycles without compromising business or quality. It necessitates good sprint management. Continuous Testing detects integration issues considerably earlier in the development process. It reduces the cost of defect resolution and frees up the tester's time for exploratory testing and value-added activities. Continuous testing allows for more frequent, shorter, and more efficient releases. It ties people, technology, and processes together. Continuous Planning, particularly effort estimation, is closely linked to Continuous Testing. This paper examines the state of the art in DevOps parametric estimate in continuous planning, as well as the difficulties and best practises. Keywords: Project, Testing, Continuous, Planning

scholarly journals Robustness Certificates for Sparse Adversarial Attacks by Randomized Ablation

2020 ◽  
Vol 34 (04) ◽  
pp. 4585-4593
Author(s):  
Alexander Levine ◽  
Soheil Feizi
Keyword(s):  
Classification Accuracy ◽  
Additive Noise ◽  
State Of The Art ◽  
Random Noise ◽  
The State ◽  
Threat Model ◽  
Robust Classification ◽  
Supplementary Material ◽  
The Cost ◽  
L1 And L2

Recently, techniques have been developed to provably guarantee the robustness of a classifier to adversarial perturbations of bounded L1 and L2 magnitudes by using randomized smoothing: the robust classification is a consensus of base classifications on randomly noised samples where the noise is additive. In this paper, we extend this technique to the L0 threat model. We propose an efficient and certifiably robust defense against sparse adversarial attacks by randomly ablating input features, rather than using additive noise. Experimentally, on MNIST, we can certify the classifications of over 50% of images to be robust to any distortion of at most 8 pixels. This is comparable to the observed empirical robustness of unprotected classifiers on MNIST to modern L0 attacks, demonstrating the tightness of the proposed robustness certificate. We also evaluate our certificate on ImageNet and CIFAR-10. Our certificates represent an improvement on those provided in a concurrent work (Lee et al. 2019) which uses random noise rather than ablation (median certificates of 8 pixels versus 4 pixels on MNIST; 16 pixels versus 1 pixel on ImageNet.) Additionally, we empirically demonstrate that our classifier is highly robust to modern sparse adversarial attacks on MNIST. Our classifications are robust, in median, to adversarial perturbations of up to 31 pixels, compared to 22 pixels reported as the state-of-the-art defense, at the cost of a slight decrease (around 2.3%) in the classification accuracy. Code and supplementary material is available at https://github.com/alevine0/randomizedAblation/.

scholarly journals Rainbow on Cortex-M4

2021 ◽  
pp. 650-675
Author(s):  
Tung Chou ◽  
Matthias J. Kannwischer ◽  
Bo-Yin Yang
Keyword(s):  
State Of The Art ◽  
The State ◽  
Constant Time ◽  
Secret Key ◽  
The Public ◽  
The Cost

We present the first Cortex-M4 implementation of the NISTPQC signature finalist Rainbow. We target the Giant Gecko EFM32GG11B which comes with 512 kB of RAM which can easily accommodate the keys of RainbowI.We present fast constant-time bitsliced F16 multiplication allowing multiplication of 32 field elements in 32 clock cycles. Additionally, we introduce a new way of computing the public map P in the verification procedure allowing vastly faster signature verification.Both the signing and verification procedures of our implementation are by far the fastest among the NISTPQC signature finalists. Signing of rainbowIclassic requires roughly 957 000 clock cycles which is 4× faster than the state of the art Dilithium2 implementation and 45× faster than Falcon-512. Verification needs about 239 000 cycles which is 5× and 2× faster respectively. The cost of signing can be further decreased by 20% when storing the secret key in a bitsliced representation.

EM-002B computer control development

1989 ◽  
Vol 47 ◽  
pp. 60-61
Author(s):  
M. Chang ◽  
T. Kamewari
Keyword(s):  
Software Package ◽  
State Of The Art ◽  
Computer Control ◽  
Hard Disk ◽  
Ultrahigh Resolution ◽  
Non Volatile Memory ◽  
Standard Configuration ◽  
Volatile Memory

The EM-002B is an ultrahigh resolution TEM with unique TEM-probe analytical capabilities. In its standard configuration, one set of lens current parameters along with 20 specimen stage XY coordinate sets can be stored in a non-volatile memory. The first stage in implementing computer control of the microscope involves extending the ability to store and recall multiple lens parameter and stage position sets.This has been accomplished by adding a standard RS-232C communications channel to the EM-002B and developing a state-of-the-art window software package to run on an IBM AT PS2 or compatible computer. This package accepts the commands from a mouse input and allows storage and automatic setting of lens current and stage position sets. After transfer to the computer parameter, sets are assigned a file name and may be stored on a floppy or hard disk. These files are easily modified and transferred via the communications channel to the EM-002B.

scholarly journals FAST Pre-Filtering-Based Real Time Road Sign Detection for Low-Cost Vehicle Localization

Sensors ◽  
2018 ◽  
Vol 18 (10) ◽  
pp. 3590 ◽  
Author(s):  
Kyoungtaek Choi ◽  
Jae Kyu Suhr ◽  
Ho Gi Jung
Keyword(s):  
Embedded System ◽  
Processing Time ◽  
State Of The Art ◽  
Low Cost ◽  
Position Estimation ◽  
The State ◽  
Vehicle Localization ◽  
Localization System ◽  
Road Sign ◽  
The Cost

In order to overcome the limitations of GNSS/INS and to keep the cost affordable for mass-produced vehicles, a precise localization system fusing the estimated vehicle positions from low-cost GNSS/INS and low-cost perception sensors is being developed. For vehicle position estimation, a perception sensor detects a road facility and uses it as a landmark. For this localization system, this paper proposes a method to detect a road sign as a landmark using a monocular camera whose cost is relatively low compared to other perception sensors. Since the inside pattern and aspect ratio of a road sign are various, the proposed method is based on the part-based approach that detects corners and combines them to detect a road sign. While the recall, precision, and processing time of the state of the art detector based on a convolutional neural network are 99.63%, 98.16%, and 4802 ms respectively, the recall, precision, and processing time of the proposed method are 97.48%, 98.78%, and 66.7 ms, respectively. The detection performance of the proposed method is as good as that of the state of the art detector and its processing time is drastically reduced to be applicable for an embedded system.

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