Non Volatile Memory Technologies: Floating Gate Concept Evolution

2004 ◽  
Vol 830 ◽  
Author(s):  
Cesare Clementi ◽  
Roberto Bez
Keyword(s):  
Data Storage ◽  
Flash Memory ◽  
Floating Gate ◽  
Nand Flash ◽  
Know How ◽  
Technology Node ◽  
Cell Architecture ◽  
Non Volatile Memory ◽  
Volatile Memory ◽  
The Cost

ABSTRACTThe most relevant phenomenon of this last decade in the field of semiconductor memories has been the explosive growth of the Flash memory market, driven by cellular phones and other types of electronic portable equipments (palm top, mobile PC, mp3 audio player, digital camera and so on). Moreover, in the coming years portable systems will ask even more non volatile memories either with high density and very high writing throughput for data storage application, or with fast random access for code execution in place. The strong consolidated know-how (more than ten years of experience), the flexibility and the cost make the floating gate Flash Memory a largely utilized, well-consolidated and mature technology for most of the non-volatile memory application. Today Flash sales represent a considerable amount of the overall semiconductor market.Nowadays two of the several cell architecture proposed up to now can be considered as industry standard: the common ground NOR Flash that due to its versatility is addressing both the code and data storage segments and the NAND Flash, optimized for the data storage market.The exploitation of the multilevel approach at each technology node allows the increase of the memory efficiency, about doubling the density at the same chip size, widening the application range and reducing the cost per bit.In this paper the main issues related to both NOR and NAND Flash memory technology will be summarized, with the aim of describing both the basic functionality of the memory cell and the main cell architecture today consolidated. Both cells are basically a floating-gate MOS transistor, programmed by channel hot electron (NOR) or by Fowler-Nordheim tunneling (NAND) and erased by Fowler-Nordheim tunnel. The main reliability properties, charge retention and endurance, are presented, together with some comments on the basic physical mechanisms responsible for.A couple of innovative approaches to floating gate cell evolution, namely nanocrystal memory and 3-D cell will be described.Finally the Flash cell scaling issues will be covered, pointing out the main challenges. The Flash cell scaling has been demonstrated to be really possible and to be able to follow the Moore's law down to the 90 nm technology generations. The technology development and the consolidated know-how are expected to sustain the scaling trend down to the 50 nm technology node and below as forecasted by the ITRS roadmap.

Read Back of Stored Data in Non Volatile Memory Devices by Scanning Capacitance Microscopy

2013 ◽  
Vol 1527 ◽  
Author(s):  
Rudra S. Dhar ◽  
St.J. Dixon-Warren ◽  
Mohamed A. Kawaliye ◽  
Jeff Campbell ◽  
Mike Green ◽  
...  
Keyword(s):  
Flash Memory ◽  
Memory Device ◽  
Floating Gate ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Floating Gates ◽  
Scanning Capacitance Microscopy ◽  
Floating Gate Transistor ◽  
Non Volatile Memory ◽  
Volatile Memory

ABSTRACTThis report outlines a methodology for reading back different electrical charges, from Non Volatile Memory (NVM) based Flash devices. The charge is stored in the floating gates (FGs) of the transistors. Reading back these charges in the form of logic levels of “1 bit (1b)” and “0 bit (0b)” without deleting the information from the device was the goal. Scanning Capacitance Microscopy (SCM) with ∼50-100 nm spatial resolution was used, to directly probe the charge on Floating Gate Transistor (FGT) channels. Transistor charge values (ON/OFF or “1b/0b”) are measured. Both the sample preparation and SCM probing methods are discussed. The application has been demonstrated with SanDisk based 64 MB NAND Flash memory device.

scholarly journals High-Performance Non-Volatile InGaZnO Based Flash Memory Device Embedded with a Monolayer Au Nanoparticles

Nanomaterials ◽  
2021 ◽  
Vol 11 (5) ◽  
pp. 1101
Author(s):  
Muhammad Naqi ◽  
Nayoung Kwon ◽  
Sung Hyeon Jung ◽  
Pavan Pujar ◽  
Hae Won Cho ◽  
...  
Keyword(s):  
Retention Time ◽  
Photoelectron Spectroscopy ◽  
Flash Memory ◽  
High Performance ◽  
Memory Window ◽  
Floating Gate ◽  
Semiconductor Layer ◽  
Non Volatile Memory ◽  
Volatile Memory ◽  
Gate Layer

Non-volatile memory (NVM) devices based on three-terminal thin-film transistors (TFTs) have gained extensive interest in memory applications due to their high retained characteristics, good scalability, and high charge storage capacity. Herein, we report a low-temperature (<100 °C) processed top-gate TFT-type NVM device using indium gallium zinc oxide (IGZO) semiconductor with monolayer gold nanoparticles (AuNPs) as a floating gate layer to obtain reliable memory operations. The proposed NVM device exhibits a high memory window (ΔVth) of 13.7 V when it sweeps from −20 V to +20 V back and forth. Additionally, the material characteristics of the monolayer AuNPs (floating gate layer) and IGZO film (semiconductor layer) are confirmed using transmission electronic microscopy (TEM), atomic force microscopy (AFM), and x-ray photoelectron spectroscopy (XPS) techniques. The memory operations in terms of endurance and retention are obtained, revealing highly stable endurance properties of the device up to 100 P/E cycles by applying pulses (±20 V, duration of 100 ms) and reliable retention time up to 104 s. The proposed NVM device, owing to the properties of large memory window, stable endurance, and high retention time, enables an excellent approach in futuristic non-volatile memory technology.

Scaling Challenges of Floating Gate Non-Volatile Memory and Graphene as the Future Flash Memory Device: A Review

2019 ◽  
Vol 14 (9) ◽  
pp. 1195-1214 ◽  
Author(s):  
Afiq Hamzah ◽  
Hilman Ahmad ◽  
Michael Loong Peng Tan ◽  
N. Ezaila Alias ◽  
Zaharah Johari ◽  
...  
Keyword(s):  
Flash Memory ◽  
Memory Device ◽  
Floating Gate ◽  
The Future ◽  
Non Volatile Memory ◽  
Volatile Memory

scholarly journals Flash memory devices with metal floating gate/metal nanocrystals as the charge storage layer: A status review

2020 ◽  
Vol 33 (2) ◽  
pp. 155-167
Author(s):  
Renu Rajput ◽  
Rakesh Vaid
Keyword(s):  
Flash Memory ◽  
Floating Gate ◽  
Tunneling Effect ◽  
Charge Storage ◽  
Memory Devices ◽  
Metal Nanocrystals ◽  
Operation Speed ◽  
Research Activities ◽  
Non Volatile Memory ◽  
Volatile Memory

Traditional flash memory devices consist of Polysilicon Control Gate (CG) - Oxide-Nitride-Oxide (ONO - Interpoly Dielectric) - Polysilicon Floating Gate (FG) - Silicon Oxide (Tunnel dielectric) - Substrate. The dielectrics have to be scaled down considerably in order to meet the escalating demand for lower write/erase voltages and higher density of cells. But as the floating gate dimensions are scaled down the charge stored in the floating gate leak out more easily via thin tunneling oxide below the floating gate which causes serious reliability issues and the whole amount of stored charge carrying information can be lost. The possible route to eliminate this problem is to use high-k based interpoly dielectric and to replace the polysilicon floating gate with a metal floating gate. At larger physical thickness, these materials have similar capacitance value hence avoiding tunneling effect. Discrete nanocrystal memory has also been proposed to solve this problem. Due to its high operation speed, excellent scalability and higher reliability it has been shown as a promising candidate for future non-volatile memory applications. This review paper focuses on the recent efforts and research activities related to the fabrication and characterization of non-volatile memory device with metal floating gate/metal nanocrystals as the charge storage layer.

PCI Express-Based NVMe Solid State Disk

2013 ◽  
Vol 464 ◽  
pp. 365-368 ◽  
Author(s):  
Ji Jun Hung ◽  
Kai Bu ◽  
Zhao Lin Sun ◽  
Jie Tao Diao ◽  
Jian Bin Liu
Keyword(s):  
Flash Memory ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Detailed Design ◽  
Pci Express ◽  
Storage Media ◽  
Solid State Disk ◽  
Memory Card ◽  
Non Volatile Memory ◽  
Flash Translation Layer

This paper presents a new architecture SSD based on NVMe (Non-Volatile Memory express) protocol. The NVMe SSD promises to solve the conventional SATA and SAS interface bottleneck. Its aimed to present a PCIe NAND Flash memory card that uses NAND Flash memory chip as the storage media. The paper analyzes the PCIe protocol and the characteristics of SSD controller, and then gives the detailed design of the PCIe SSD. It mainly contains the PCIe port and Flash Translation Layer.

Quantum Dot Gate (QDG) Quantum Dot Channel (QDC) Multistate Logic Non-Volatile Memory (NVM) with High-K Dielectric HfO2 Barriers

2020 ◽  
Vol 29 (01n04) ◽  
pp. 2040001
Author(s):  
N. R. Butterfield ◽  
R. Mays ◽  
B. Khan ◽  
R. Gudlavalleti ◽  
F. C. Jain
Keyword(s):  
Quantum Dot ◽  
Hafnium Oxide ◽  
Experimental Testing ◽  
Memory Cell ◽  
Floating Gate ◽  
Carrier Injection ◽  
High K ◽  
Non Volatile Memory ◽  
Volatile Memory ◽  
High K Dielectric

This paper presents the theory, fabrication and experimental testing results for a multiple state Non-Volatile Memory (NVM), comprised of hafnium oxide high-k dielectric tunnel and gate barriers as well as a Silicon Quantum Dot Superlattice (QDSL) implemented for the floating gate and inversion channel (QDG) and (QDC) respectively. With the conclusion of Moore’s Law for conventional transistor fabrication, regarding the minimum gate size, current efforts in memory cell research and development are focused on bridging the gap between the conventions of the past sixty years and the future of computing. One method of continuing the increasing chip density is to create multistate devices capable of storing and processing additional logic states beyond 1 and 0. Replacing the silicon nitride floating gate of a conventional Flash NVM with QDSL gives rise to minibands that result in greater control over charge levels stored in the QDG and additional intermediate states. Utilizing Hot Carrier Injection (HCI) programming, for the realized device, various magnitudes of gate voltage pulses demonstrated the ability to accurately control the charge levels stored in the QDG. This corresponds to multiple threshold voltage shifts allowing detection of multiple states during read operations.

scholarly journals ZDC: A Zone Data Compression Method for Solid State Drive Based Flash Memory

Symmetry ◽  
2020 ◽  
Vol 12 (4) ◽  
pp. 623
Author(s):  
Xin Ye ◽  
Zhengjun Zhai ◽  
Xiaochang Li
Keyword(s):  
Solid State ◽  
Data Compression ◽  
Data Storage ◽  
Flash Memory ◽  
Research Result ◽  
Nand Flash ◽  
Data Deduplication ◽  
Solid State Drive ◽  
Research Results ◽  
Hot Zone

Solid-state drive (SSD) with flash memory as the storage medium are being widely used in various data storage systems. SSD data compression means that data is compressed before it is written to Not-And (NAND) Flash. Data compression can reduce the amount of data written in NAND Flash and improve the performance and reliability of SSDs. At present, the main problem facing data compression of SSD is how to improve the efficiency of data compression and decompression. In order to improve the performance of data compression and decompression, this study proposes a method of SSD data deduplication based on zone division. First, this study divides the storage space of the SSD into zones and divides them into one hot zone and multiple cold zones according to the different erasing frequency. Second, the data in each zone is divided into hot data and cold data according to the number of erasures. At the same time, the address mapping table in the hot zone is loaded into the cache. Finally, when there is a write or read request, the SSD will selectively compress or decompress the data according to the type of different zones. Through simulation tests, the correctness and effectiveness of this study are verified. The research results show that the data compression rate of this research result can reach 70–95%. Compared with SSD without data compression, write amplification is reduced by 5 to 30%, and write latency is reduced by 5 to 25%. The research results have certain reference value for improving the performance and reliability of SSD.

7.7 A 768Gb 3b/cell 3D-floating-gate NAND flash memory

2016 ◽  
Author(s):  
Tomoharu Tanaka ◽  
Mark Helm ◽  
Tommaso Vali ◽  
Ramin Ghodsi ◽  
Koichi Kawai ◽  
...  
Keyword(s):  
Flash Memory ◽  
Floating Gate ◽  
Nand Flash ◽  
Nand Flash Memory

Unified Endurance Degradation Model of Floating Gate NAND Flash Memory

2013 ◽  
Vol 60 (6) ◽  
pp. 2031-2037 ◽  
Author(s):  
Albert Fayrushin ◽  
Chang-Hyun Lee ◽  
Youngwoo Park ◽  
Jeong-Hyuk Choi ◽  
Chilhee Chung
Keyword(s):  
Flash Memory ◽  
Floating Gate ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Degradation Model
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