(Invited) Parylene C Based Adhesive Bonding on 6” and 8” Wafer Level for the Realization of Highly Reliable and Fully Biocompatible Microsystems

ABSTRACTA monolithic, wafer-level three-dimensional (3D) technology platform is described that is compatible with next-generation wafer level packaging (WLP) processes. The platform combines the advantages of both (1) high bonding strength and adaptability to IC wafer topography variations with spin-on dielectric adhesive bonding and (2) process integration and via-area advantages of metal-metal bonding. A copper-benzocyclobutene (Cu-BCB) process is described that incorporates single-level damascene-patterned Cu vias with partially-cured BCB as the bonding adhesive layer. A demonstration vehicle consisting of a two-wafer stack of 2-4 μm diameter vias has shown the bondability of both Cu-to-Cu and BCB-to-BCB. Planarization conditions to achieve BCB-BCB bonding with low-resistance Cu-Cu contacts have been examined, with wafer-scale planarization requirements compared to other 3D platforms. Concerns about stress induced at the tantalum (Ta) liner-to-BCB interface resulting in partial delamination are discussed. While across-wafer uniformity has not been demonstrated, the viability of this WLP-compatible 3D platform has been shown.

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Area-Selective Adhesive Bonding Using Photosensitive BCB for WL CSP Applications

Journal of Electronic Packaging ◽

10.1115/1.1846059 ◽

2005 ◽

Vol 127 (1) ◽

pp. 7-11 ◽

Cited By ~ 13

Author(s):

A. Polyakov ◽

M. Bartek ◽

J. N. Burghartz

Keyword(s):

Fracture Toughness ◽

Tensile Strength ◽

Wafer Bonding ◽

Potential Application ◽

Adhesive Bonding ◽

Wafer Level ◽

Chip Scale Package ◽

Rf Applications

This paper reports on an area-selective adhesive wafer bonding, using photosensitive BCB from Dow Co. The strength of the fabricated bonds is characterized using the wedge-opening and tensile methods. The measured fracture toughness is 53.5±3.9J/m2 with tensile strength up to 71 MPa. The potential application of BCB bonding is demonstrated on a concept of wafer-level chip-scale package for RF applications and microfilter array for microfluidic applications.

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Temporary handling technology for advanced wafer level packaging applications based on adhesive bonding and laser assisted de-bonding

2014 IEEE 16th Electronics Packaging Technology Conference (EPTC) ◽

10.1109/eptc.2014.7028324 ◽

2014 ◽

Cited By ~ 3

Author(s):

Kai Zoschke ◽

Thorsten Fischer ◽

Hermann Oppermann ◽

Klaus-Dieter Lang

Keyword(s):

Adhesive Bonding ◽

Wafer Level ◽

Wafer Level Packaging

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Development of high throughput adhesive bonding scheme by wafer-level underfill for 3D die-to-interposer stacking with 30µm-pitch micro interconnections

2015 IEEE 65th Electronic Components and Technology Conference (ECTC) ◽

10.1109/ectc.2015.7159636 ◽

2015 ◽

Cited By ~ 4

Author(s):

Yu-Wei Huang ◽

Chia-Wen Fan ◽

Yu-Min Lin ◽

Su-Yu Fun ◽

Su-Ching Chung ◽

...

Keyword(s):

High Throughput ◽

Adhesive Bonding ◽

Wafer Level ◽

Bonding Scheme

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Integration Technology for Wafer-Level LiNbO3 Single-Crystal Thin Film on Silicon by Polyimide Adhesive Bonding and Chemical Mechanical Polishing

Nanomaterials ◽

10.3390/nano11102554 ◽

2021 ◽

Vol 11 (10) ◽

pp. 2554

Author(s):

Wenping Geng ◽

Xiangyu Yang ◽

Gang Xue ◽

Wenhao Xu ◽

Kaixi Bi ◽

...

Keyword(s):

Thin Film ◽

Single Crystal ◽

Chemical Mechanical Polishing ◽

Adhesive Bonding ◽

Mechanical Polishing ◽

Bonding Interface ◽

Infrared Analysis ◽

Mems Devices ◽

Wafer Level ◽

Integration Technology

An integration technology for wafer-level LiNbO3 single-crystal thin film on Si has been achieved. The optimized spin-coating speed of PI (polyimide) adhesive is 3500 rad/min. According to Fourier infrared analysis of the chemical state of the film baked under different conditions, a high-quality PI film that can be used for wafer-level bonding is obtained. A high bonding strength of 11.38 MPa is obtained by a tensile machine. The bonding interface is uniform, completed and non-porous. After the PI adhesive bonding process, the LiNbO3 single-crystal was lapped by chemical mechanical polishing. The thickness of the 100 mm diameter LiNbO3 can be decreased from 500 to 10 μm without generating serious cracks. A defect-free and tight bonding interface was confirmed by scanning electron microscopy. X-ray diffraction results show that the prepared LiNbO3 single-crystal thin film has a highly crystalline quality. Heterogeneous integration of LiNbO3 single-crystal thin film on Si is of great significance to the fabrication of MEMS devices for in-situ measurement of space-sensing signals.

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Wafer-Level 3D Integration Based on Poly (Diallyl Phthalate) Adhesive Bonding

Micromachines ◽

10.3390/mi12121586 ◽

2021 ◽

Vol 12 (12) ◽

pp. 1586

Author(s):

Zhong Fang ◽

Peng You ◽

Yijie Jia ◽

Xuchao Pan ◽

Yunlei Shi ◽

...

Keyword(s):

Adhesive Bonding ◽

Low Cost ◽

Three Dimensional ◽

System Level ◽

Process Conditions ◽

Wafer Level ◽

3D Integration ◽

Bonding Pressure ◽

Curing Conditions ◽

Integration Technology

Three-dimensional integration technology provides a promising total solution that can be used to achieve system-level integration with high function density and low cost. In this study, a wafer-level 3D integration technology using PDAP as an intermediate bonding polymer was applied effectively for integration with an SOI wafer and dummy a CMOS wafer. The influences of the procedure parameters on the adhesive bonding effects were determined by Si–Glass adhesive bonding tests. It was found that the bonding pressure, pre-curing conditions, spin coating conditions, and cleanliness have a significant influence on the bonding results. The optimal procedure parameters for PDAP adhesive bonding were obtained through analysis and comparison. The 3D integration tests were conducted according to these optimal parameters. In the tests, process optimization was focused on Si handle-layer etching, PDAP layer etching, and Au pillar electroplating. After that, the optimal process conditions for the 3D integration process were achieved. The 3D integration applications of the micro-bolometer array and the micro-bridge resistor array were presented. It was confirmed that 3D integration based on PDAP adhesive bonding is suitable for the fabrication of system-on-chip when using MEMS and IC integration and that it is especially useful for the fabrication of low-cost suspended-microstructure on-CMOS-chip systems.

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Wafer Level Package for MEMS with TSVs and Hermetic Seal

Additional Conferences (Device Packaging HiTEC HiTEN & CICMT) ◽

10.4071/2011dpc-tha24 ◽

2011 ◽

Vol 2011 (DPC) ◽

pp. 002314-002335

Author(s):

Akinori Shiraishi ◽

Mitsutoshi Higashi ◽

Kei Murayama ◽

Yuichi Taguchi ◽

Kenichi Mori

Keyword(s):

Silicon Wafer ◽

Adhesive Bonding ◽

Anodic Bonding ◽

Back Side ◽

Wafer Level ◽

Wafer Level Packaging ◽

Hermetic Seal ◽

Mems Device ◽

Bonding Method ◽

Wafer Level Package

In recent years, downsizing of MEMS package and high accuracy MEMS device mounting have been strongly required from expanding applications that using MEMS not only for industrial and automobile but also for consumer typified mobile phone. In order to achieve that, it is appropriate to use Silicon package that can be mounted at wafer level packaging. Silicon package is made of monocrystal silicon wafer. The deep cavity is fabricated on monocrystal silicon wafer by Wet or Dry etching. And MEMS device can be mounted on the cavity. The electrical connecting between front side and back side of cavity portion is achieved by TSVs that located on the bottom of cavity. Hermetic seal can be achieved by using glass or silicon wafer bonding method. By using a driver device wafer (before dicing) as the cap for hermetic seal, smaller size and smaller number of parts module can be fabricated. In this report, methods and designs for hermetic seal with wafer level process were examined. Methods that applied were polyimide adhesive bonding, anodic bonding and Au-In solder bonding. Location of TSVs on the bottom of cavity and thickness of diaphragm with TSVs was also examined. Silicon package for piezo type gyro MEMS that designed by the result of evaluation was fabricated. This package used optimized Au-In solder bonding for hermetic seal and optimized location of TSVs for interconnection. That was designed over 50% thinner than conventional ceramic packages. Characteristics of hermetic seal were evaluated by Q factor of gyro MEMS that mounted inside of the silicon package. It is confirmed that performance of sealing are good enough for running of the MEMS.

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