scholarly journals Wafer-Level 3D Integration Based on Poly (Diallyl Phthalate) Adhesive Bonding

Micromachines ◽  
2021 ◽  
Vol 12 (12) ◽  
pp. 1586
Author(s):  
Zhong Fang ◽  
Peng You ◽  
Yijie Jia ◽  
Xuchao Pan ◽  
Yunlei Shi ◽  
...  

Three-dimensional integration technology provides a promising total solution that can be used to achieve system-level integration with high function density and low cost. In this study, a wafer-level 3D integration technology using PDAP as an intermediate bonding polymer was applied effectively for integration with an SOI wafer and dummy a CMOS wafer. The influences of the procedure parameters on the adhesive bonding effects were determined by Si–Glass adhesive bonding tests. It was found that the bonding pressure, pre-curing conditions, spin coating conditions, and cleanliness have a significant influence on the bonding results. The optimal procedure parameters for PDAP adhesive bonding were obtained through analysis and comparison. The 3D integration tests were conducted according to these optimal parameters. In the tests, process optimization was focused on Si handle-layer etching, PDAP layer etching, and Au pillar electroplating. After that, the optimal process conditions for the 3D integration process were achieved. The 3D integration applications of the micro-bolometer array and the micro-bridge resistor array were presented. It was confirmed that 3D integration based on PDAP adhesive bonding is suitable for the fabrication of system-on-chip when using MEMS and IC integration and that it is especially useful for the fabrication of low-cost suspended-microstructure on-CMOS-chip systems.

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 1-20
Author(s):  
Geun Sik Kim ◽  
Kai Liu ◽  
Flynn Carson ◽  
Seung Wook Yoon ◽  
Meenakshi Padmanathan

IPD technology was originally developed as a way to replace bulky discrete passive components, but it¡¯s now gaining popularity in ESD/EMI protection applications, as well as in RF, high-brightness LED silicon sub-mounts, and digital and mixed-signal devices. Already well known as a key enabler of system-in-packages (SiPs), IPDs enable the assembly of increasingly complete and autonomous systems with the integration of diverse electronic functions such as sensors, RF transceivers, MEMS, power amplifiers, power management units, and digital processors. The application area for IPD will continue to evolve, especially as new packaging technology, such as flipchip, 3D stacking, wafer level packaging become available to provide vertical interconnections within the IPD. New applications like silicon interposers will become increasingly significant to the market. Currently the IPD market is being driven primarily by RF or wireless packages and applications including, but not limited to, cell phones, WiFi, GPS, WiMAX, and WiBro. In particular, applications and products in the emerging RF CMOS market that require a low cost, smaller size, and high performance are driving demand. In order to get right products in size and performance, packaging design and technology should be considered in device integration and implemented together in IPD designs. In addition, a comprehensive understanding of electrical and mechanical properties in component and system level design is important. This paper will highlight some of the recent advancements in SiP technology for IPD and integration as well as what is developed to address future technology requirements in IPD SiP solutions. The advantage and applications of SiP solution for IPD will be presented with several examples of IPD products. The design, assembly and packaging challenges and performance characteristics will be also discussed.


Author(s):  
Raquel Pinto ◽  
André Cardoso ◽  
Sara Ribeiro ◽  
Carlos Brandão ◽  
João Gaspar ◽  
...  

Microelectromechanical Systems (MEMS) are a fast growing technology for sensor and actuator miniaturization finding more and more commercial opportunities by having an important role in the field of Internet of Things (IoT). On the same note, Fan-out Wafer Level Packaging (FOWLP), namely WLFO technology of NANIUM, which is based on Infineon/ Intel eWLB technology, is also finding further applications, not only due to its high performance, low cost, high flexibility, but also due to its versatility to allow the integration of different types of components in the same small form-factor package. Despite its great potential it is still off limits to the more sensitive components as micro-mechanical devices and some type of sensors, which are vulnerable to temperature and pressure. In the interest of increasing FOWLP versatility and enabling the integration of MEMS, new methods of assembling and processing are continuously searched for. Dielectrics currently used for redistribution layer construction need to be cured at temperatures above 200°C, making it one of the major boundary for low temperature processing. In addition, in order to accomplish a wide range of dielectric thicknesses in the same package it is often necessary to stack very different types of dielectrics with impact on bill of materials complexity and cost. In this work, done in cooperation with the International Iberian Nanotechnology Laboratory (INL), we describe the implementation of commercially available SU-8 photoresist as a structural material in FOWLP, allowing lower processing temperature and reduced internal package stress, thus enabling the integration of components such as MEMS/MOEMS, magneto-resistive devices and micro-batteries. While SU-8 photoresist was first designed for the microelectronics industry, it is currently highly used in the fabrication of microfluidics as well as microelectromechanical systems (MEMS) and BIO-MEMS due to its high biocompatibility and wide range of available thicknesses in the same product family. Its good thermal and chemical resistance and also mechanical and rheological properties, make it suitable to be used as a structural material, and moreover it cures at 150°C, which is key for the applications targeted. Unprecedentedly, SU-8 photoresist is tested in this work as a structural dielectric for the redistribution layers on 300mm fan-out wafers. Main concerns during the evaluation of the new WLFO dielectric focused on processability quality; adhesion to multi-material substrate and metals (copper, aluminium, gold, ¦); between layers of very different thicknesses; and overall reliability. During preliminary runs, processability on 300 mm fan-out wafers was evaluated by testing different coating and soft bake conditions, exposure settings, post-exposure parameters, up to developing setup. The outputs are not only on process conditions and results but also on WLFO design rules. For the first time, a set of conditions has been defined that allows processing SU-8 on WLFO, with thickness values ranging from 1 um to 150 um. The introduction of SU-8 in WLFO is a breakthrough in this fast-growing advanced packaging technology platform as it opens vast opportunities for sensor integration in WLP technology.


2010 ◽  
Vol 2010 (1) ◽  
pp. 000548-000553
Author(s):  
Zhaozhi Li ◽  
Brian J. Lewis ◽  
Paul N. Houston ◽  
Daniel F. Baldwin ◽  
Eugene A. Stout ◽  
...  

Three Dimensional (3D) Packaging has become an industry obsession as the market demand continues to grow toward higher packaging densities and smaller form factor. In the meanwhile, the 3D die-to-wafer (D2W) packaging structure is gaining popularity due to its high manufacturing throughput and low cost per package. In this paper, the development of the assembly process for a 3D die-to-wafer packaging technology, that leverages the wafer level assembly technique and flip chip process, is introduced. Research efforts were focused on the high-density flip chip wafer level assembly techniques, as well as the challenges, innovations and solutions associated with this type of 3D packaging technology. Processing challenges and innovations addressed include flip chip fluxing methods for very fine-pitch and small bump sizes; wafer level flip chip assembly program creation and yield improvements; and set up of the Pb-free reflow profile for the assembled wafer. 100% yield was achieved on the test vehicle wafer that has totally 1,876 flip chip dies assembled on it. This work has demonstrated that the flip chip 3D die-to-wafer packaging architecture can be processed with robust yield and high manufacturing throughput, and thus to be a cost effective, rapid time to market alternative to emerging 3D wafer level integration methodologies.


2006 ◽  
Vol 970 ◽  
Author(s):  
Ronald J. Gutmann ◽  
J. Jay McMahon ◽  
Jian-Qiang Lu

ABSTRACTA monolithic, wafer-level three-dimensional (3D) technology platform is described that is compatible with next-generation wafer level packaging (WLP) processes. The platform combines the advantages of both (1) high bonding strength and adaptability to IC wafer topography variations with spin-on dielectric adhesive bonding and (2) process integration and via-area advantages of metal-metal bonding. A copper-benzocyclobutene (Cu-BCB) process is described that incorporates single-level damascene-patterned Cu vias with partially-cured BCB as the bonding adhesive layer. A demonstration vehicle consisting of a two-wafer stack of 2-4 μm diameter vias has shown the bondability of both Cu-to-Cu and BCB-to-BCB. Planarization conditions to achieve BCB-BCB bonding with low-resistance Cu-Cu contacts have been examined, with wafer-scale planarization requirements compared to other 3D platforms. Concerns about stress induced at the tantalum (Ta) liner-to-BCB interface resulting in partial delamination are discussed. While across-wafer uniformity has not been demonstrated, the viability of this WLP-compatible 3D platform has been shown.


2004 ◽  
Vol 843 ◽  
Author(s):  
J. Yu ◽  
J. J. McMahon ◽  
J.-Q. Lu ◽  
R. J. Gutmann

ABSTRACTWafer level monolithic three-dimensional (3D) integration is an emerging technology to realize enhanced performance and functionality with reduced form-factor and manufacturing cost. The cornerstone for this 3D processing technology is full-wafer bonding under back-end-of-the-line (BEOL) compatible process conditions. For the first time to our knowledge, we demonstrate nearly void-free 200 mm wafer-to-wafer bonding with an ultra-thin Ti adhesive coating, annealed at BEOL-compatible temperature (400 °C) in vacuum with external pressure applied. Mechanical integrity test showed that bonded wafer pair survived after a stringent three-step thinning process (grinding/polishing/wet-etching) with complete removal of top Si wafer, while allowing optical inspection of bonding interface. Mechanisms contributing to the strong bonding at Ti/Si interface are briefly discussed.


Nanomaterials ◽  
2021 ◽  
Vol 11 (10) ◽  
pp. 2554
Author(s):  
Wenping Geng ◽  
Xiangyu Yang ◽  
Gang Xue ◽  
Wenhao Xu ◽  
Kaixi Bi ◽  
...  

An integration technology for wafer-level LiNbO3 single-crystal thin film on Si has been achieved. The optimized spin-coating speed of PI (polyimide) adhesive is 3500 rad/min. According to Fourier infrared analysis of the chemical state of the film baked under different conditions, a high-quality PI film that can be used for wafer-level bonding is obtained. A high bonding strength of 11.38 MPa is obtained by a tensile machine. The bonding interface is uniform, completed and non-porous. After the PI adhesive bonding process, the LiNbO3 single-crystal was lapped by chemical mechanical polishing. The thickness of the 100 mm diameter LiNbO3 can be decreased from 500 to 10 μm without generating serious cracks. A defect-free and tight bonding interface was confirmed by scanning electron microscopy. X-ray diffraction results show that the prepared LiNbO3 single-crystal thin film has a highly crystalline quality. Heterogeneous integration of LiNbO3 single-crystal thin film on Si is of great significance to the fabrication of MEMS devices for in-situ measurement of space-sensing signals.


2018 ◽  
Vol 47 (12) ◽  
pp. 7544-7557 ◽  
Author(s):  
Mingjun Yao ◽  
Ning Zhao ◽  
Teng Wang ◽  
Daquan Yu ◽  
Zhiyi Xiao ◽  
...  

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