Damascene-Patterned Metal-Adhesive (Cu-BCB) Redistribution Layers

2006 ◽  
Vol 970 ◽  
Author(s):  
Ronald J. Gutmann ◽  
J. Jay McMahon ◽  
Jian-Qiang Lu
Keyword(s):  
Bonding Strength ◽  
Adhesive Bonding ◽  
Process Integration ◽  
Three Dimensional ◽  
Adhesive Layer ◽  
Wafer Level ◽  
Technology Platform ◽  
Metal Bonding ◽  
Wafer Level Packaging ◽  
Metal Metal

ABSTRACTA monolithic, wafer-level three-dimensional (3D) technology platform is described that is compatible with next-generation wafer level packaging (WLP) processes. The platform combines the advantages of both (1) high bonding strength and adaptability to IC wafer topography variations with spin-on dielectric adhesive bonding and (2) process integration and via-area advantages of metal-metal bonding. A copper-benzocyclobutene (Cu-BCB) process is described that incorporates single-level damascene-patterned Cu vias with partially-cured BCB as the bonding adhesive layer. A demonstration vehicle consisting of a two-wafer stack of 2-4 μm diameter vias has shown the bondability of both Cu-to-Cu and BCB-to-BCB. Planarization conditions to achieve BCB-BCB bonding with low-resistance Cu-Cu contacts have been examined, with wafer-scale planarization requirements compared to other 3D platforms. Concerns about stress induced at the tantalum (Ta) liner-to-BCB interface resulting in partial delamination are discussed. While across-wafer uniformity has not been demonstrated, the viability of this WLP-compatible 3D platform has been shown.

MC4:  A Hypothetical Three-Dimensional Organometallic Net with Metal−Metal Bonding and Polyacetylene Substructures

1996 ◽  
Vol 118 (42) ◽  
pp. 10294-10302 ◽  
Author(s):  
Norman Goldberg ◽  
Huang Tang ◽  
Nancy Kroohs ◽  
Roald Hoffmann
Keyword(s):  
Three Dimensional ◽  
Metal Bonding ◽  
Metal Metal

scholarly journals A FULL-SCALE STUDY OF THE STRENGTH OF MASSIVE WOOD GLUING WITH MODERN ADHESIVES WHEN OPERATING IN VARIOUS CONDITIONS

2020 ◽  
Vol 10 (1) ◽  
pp. 105-115
Author(s):  
Larisa Ponomarenko ◽  
Ekaterina Kantieva ◽  
Maksim Posluhaev ◽  
Aleksandr Chernyshev
Keyword(s):  
Bonding Strength ◽  
Polyvinyl Acetate ◽  
Adhesive Bonding ◽  
Adhesive Layer ◽  
Correct Choice ◽  
Operating Conditions ◽  
Furniture Manufacturing ◽  
Wooden House ◽  
House Building ◽  
Adhesive Materials

Abstract Glues are widely used to connect various materials, especially since in some cases other options for combining materials are not suitable. The paper deals with the bonding of solid hardwood with modern adhesive materials. Currently, a large group of adhesives of various brands from Russian and foreign manufacturers is presented on the market. In the woodworking industry, adhesives are used in the carpentry and furniture, manufacturing, in wooden house-building, in the production of finishing materials, etc., which are operated outside and inside the premises in constant and variable humidity conditions. Therefore, the correct choice of adhesives plays an important role both for the manufacturer and subsequently for the consumer of the resulting product. In this work, we have studied the dependence of the tensile strength when chipping along the adhesive layer on the type of glue, wood species, and operating conditions. We have selected the following adhesives based on polychloroprene, polyvinyl acetate and rubber. The greatest strength of the adhesive bonding when gluing solid hardwood is given by polyvinyl acetate adhesives. When using the product in conditions of changing temperature and humidity, the bonding strength decreases, in some cases significantly. In fairness, it should be noted that not only the type of glue, but also the type of wood affects the bonding strength

Structural Nanocomposite Bonding Reinforced by Graphite Nanofibers with Surface Treatments

2004 ◽  
Vol 843 ◽  
Author(s):  
L. Roy Xu ◽  
Charles M. Lukehart ◽  
Lang Li ◽  
Sreeparna Sengupta ◽  
Ping Wang
Keyword(s):  
Bonding Strength ◽  
Adhesive Bonding ◽  
Covalent Binding ◽  
Strength Increase ◽  
Thermal Curing ◽  
Graphite Nanofibers ◽  
Shear Joint ◽  
Metal Metal ◽  
Graphitic Carbon Nanofibers ◽  
Linker Molecules

ABSTRACTGraphitic carbon nanofibers were used to reinforce epoxy resin to form nanocomposite adhesive bonding. GCNFs having a herringbone atomic structure are surface-derivatized with bifunctional hexanediamine linker molecules capable of covalent binding to an epoxy matrix during thermal curing and are cut to smaller dimension using ultrasonication. Good dispersion and polymer wetting of the GCNF component is evident on the nanoscale. Tensile and shear joint strength measurements were conducted for metal-metal and polymer-polymer joints using pure epoxy and nanocomposite bonding. Very little bonding strength increase, or some bonding strength decrease, was measured.

scholarly journals Wafer-Level 3D Integration Based on Poly (Diallyl Phthalate) Adhesive Bonding

Micromachines ◽  
2021 ◽  
Vol 12 (12) ◽  
pp. 1586
Author(s):  
Zhong Fang ◽  
Peng You ◽  
Yijie Jia ◽  
Xuchao Pan ◽  
Yunlei Shi ◽  
...  
Keyword(s):  
Adhesive Bonding ◽  
Low Cost ◽  
Three Dimensional ◽  
System Level ◽  
Process Conditions ◽  
Wafer Level ◽  
3D Integration ◽  
Bonding Pressure ◽  
Curing Conditions ◽  
Integration Technology

Three-dimensional integration technology provides a promising total solution that can be used to achieve system-level integration with high function density and low cost. In this study, a wafer-level 3D integration technology using PDAP as an intermediate bonding polymer was applied effectively for integration with an SOI wafer and dummy a CMOS wafer. The influences of the procedure parameters on the adhesive bonding effects were determined by Si–Glass adhesive bonding tests. It was found that the bonding pressure, pre-curing conditions, spin coating conditions, and cleanliness have a significant influence on the bonding results. The optimal procedure parameters for PDAP adhesive bonding were obtained through analysis and comparison. The 3D integration tests were conducted according to these optimal parameters. In the tests, process optimization was focused on Si handle-layer etching, PDAP layer etching, and Au pillar electroplating. After that, the optimal process conditions for the 3D integration process were achieved. The 3D integration applications of the micro-bolometer array and the micro-bridge resistor array were presented. It was confirmed that 3D integration based on PDAP adhesive bonding is suitable for the fabrication of system-on-chip when using MEMS and IC integration and that it is especially useful for the fabrication of low-cost suspended-microstructure on-CMOS-chip systems.

Enabling Resist Processing Technologies for Advanced Packaging

2014 ◽  
Vol 2014 (DPC) ◽  
pp. 000830-000862 ◽  
Author(s):  
Antun Peic ◽  
Thorsten Matthias ◽  
Johanna Bartl ◽  
Paul Lindner
Keyword(s):  
Three Dimensional ◽  
Design Solution ◽  
Wafer Level ◽  
Coating Technology ◽  
3D Ic ◽  
Wafer Level Packaging ◽  
Aspect Ratios ◽  
Integration Schemes ◽  
Interconnect Design ◽  
Deep Cavities

The increasing adoption of advanced wafer-level packaging (WLP) technologies and high density interposer concepts clearly reflect the permanent need for form factor reduction, smaller process geometries and higher-count I/O on ICs. Currently, several strategies are being pursued to achieve these goals. The most promising approaches are summarized under the concept of three-dimensional integrated circuits (3D-IC) and three-dimensional wafer level packaging (3D-WLP) technology. A key component for 3D device integration schemes is the requirement of vertical through-silicon-via (TSV) interconnections that enables electrical through-chip communication through stacks of vertically integrated layers on the wafer scale. Ultimately, the use of TSVs also enables higher performance and smaller package sizes. In order to realize TSV connections, a series of process steps is required such as the thinning and bonding of the wafer to a carrier prior to the formation of through-wafer vias, followed by the passivation and metallization of the vias. Despite the potential benefits associated with the integration of TSVs also significant challenges have to be overcome. One of the greatest challenges for present and even more for upcoming TSV design strategies still remains the processing of photoresist and other functional polymers at and within TSV geometries. To this day, it is still very difficult to achieve a conformal polymer coating in deep cavities, along steep side walls and especially within the extreme aspect ratios of TSV. Mainly this is due to the fact that standard surface coating methods such as spin coating were just not developed to meet the requirements posed by these high aspect ratio microstructures. New and innovative approaches are needed to meet these new challenges. Spray coating is one of the most promising technologies to overcome current barriers. However, even most of the available spray deposition equipment is facing its limits with steadily decreasing via diameters and increasing aspect ratios on the other hand. Successively, the multitude of these challenging technological developments in the 3D-IC and wafer-level packaging area has created the demand for innovative manufacturing approaches, new equipment and related tools. Herein we present our new EVG ®NanoSprayTM coating technology with unique capabilities to overcome the present limits of conformal resist coating over extreme topography. We demonstrate one particularly promising application for conformal polymer coatings; as an annular lining at the interface between the conducting metal filling in the TSV and the silicon wafer. The intrinsic properties of the polymer allow a TSV design solution that is more forgiving on coefficient of thermal expansion (CTE) mismatch-induced stress between the silicon substrate and the interfacing metal. Consequently, this new type of polymer buffered TSV interconnect design promises to significantly reduce thermal stress-induced TSV delamination as one of the dominant failure modes for 3-D interconnects. We further demonstrate the application of EVG ®NanoSprayTM as enabling coating technology for llithographic processing of conformal coated TSVs. The patterning of thin photoresist layers at the bottom of vias and along the steep sidewalls of deep cavities allows for more degrees of freedom in electrical contact formation. The presented EVG ®NanoSprayTM coating technology opens new dimensions in advanced wafer level packaging and provokes reconsidering prevailing limitations in interconnect design.

Wafer Level Package for MEMS with TSVs and Hermetic Seal

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 002314-002335
Author(s):  
Akinori Shiraishi ◽  
Mitsutoshi Higashi ◽  
Kei Murayama ◽  
Yuichi Taguchi ◽  
Kenichi Mori
Keyword(s):  
Silicon Wafer ◽  
Adhesive Bonding ◽  
Anodic Bonding ◽  
Back Side ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Hermetic Seal ◽  
Mems Device ◽  
Bonding Method ◽  
Wafer Level Package

In recent years, downsizing of MEMS package and high accuracy MEMS device mounting have been strongly required from expanding applications that using MEMS not only for industrial and automobile but also for consumer typified mobile phone. In order to achieve that, it is appropriate to use Silicon package that can be mounted at wafer level packaging. Silicon package is made of monocrystal silicon wafer. The deep cavity is fabricated on monocrystal silicon wafer by Wet or Dry etching. And MEMS device can be mounted on the cavity. The electrical connecting between front side and back side of cavity portion is achieved by TSVs that located on the bottom of cavity. Hermetic seal can be achieved by using glass or silicon wafer bonding method. By using a driver device wafer (before dicing) as the cap for hermetic seal, smaller size and smaller number of parts module can be fabricated. In this report, methods and designs for hermetic seal with wafer level process were examined. Methods that applied were polyimide adhesive bonding, anodic bonding and Au-In solder bonding. Location of TSVs on the bottom of cavity and thickness of diaphragm with TSVs was also examined. Silicon package for piezo type gyro MEMS that designed by the result of evaluation was fabricated. This package used optimized Au-In solder bonding for hermetic seal and optimized location of TSVs for interconnection. That was designed over 50% thinner than conventional ceramic packages. Characteristics of hermetic seal were evaluated by Q factor of gyro MEMS that mounted inside of the silicon package. It is confirmed that performance of sealing are good enough for running of the MEMS.

3D & System-in-Package Development with the Redistributed Chip Package (RCP)

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 002374-002398
Author(s):  
Zhiwei (Tony) Gong ◽  
Scott Hayes ◽  
Navjot Chhabra ◽  
Trung Duong ◽  
Doug Mitchell ◽  
...  
Keyword(s):  
Three Dimensional ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Systems On Chip ◽  
3D Packaging ◽  
Packaging Space ◽  
Advanced Packaging ◽  
On Chip ◽  
Imaging Sensors ◽  
3D Applications

Fan-out wafer level packaging (FO-WLP) has become prevalent in past two years as a package option with large number of pin count. As the result of early development, the single die packages with single-sided redistribution has reached the maturity to take off. While the early applications start to pay back the investment on the technology, the developments have shifted to more advanced packaging solutions with System-in-Package (SiP) and 3D applications. The nature of the FO-WLP interconnect along with the material compatibility and process capability of the Redistributed Chip Package (RCP) have enabled Freescale to create novel System-in-Package (SiP) solutions not possible in more traditional packaging technologies or Systems-on-Chip. Simple SiPs using two dimensional (2D), multi-die RCP solutions have resulted in significant package size reduction and improved system performance through shortened traces when compared to discretely packaged die or a substrate based multi-chip module (MCM). More complex three dimensional (3D) SiP solutions allow for even greater volumetric efficiency of the packaging space. 3D RCP is a flexible approach to 3D packaging with complexity ranging from Package-on-Package (PoP) type solutions to systems including ten or more multi-sourced die with associated peripheral components. Perhaps the most significant SiP capability of the RCP technology is the opportunity for heterogeneous integration. The combination of various system elements including, but not limited to SMDs, CMOS, GaAs, MEMS, imaging sensors or IPDs gives system designers the capability to generate novel systems and solutions which can then enable new products for customers. The following paper further discusses SiP advantages, applications and examples created with the RCP technology. Rozalia/Ron ok move from 2.5/3D to Passive 1-4-12.

Sign in / Sign up

Export Citation Format

Share Document