Unusual Threshold Voltage Shift Caused by Self-Heating-Induced Charge Trapping Effect

A stochastic model of gamma-ray radiation effects on the density of the induced charge in silicon dioxide films of MOS transistors is presented in this paper. It is assumed that both radiation induced charge generation and trapped charge recombination are stochastic processes. For estimating gamma-ray induced charges spatially distributed in silicon dioxide films, a procedure similar to the Monte Carlo method was used. The proposed model implemented in the programming language MATHEMATICA enables us, for the first time, to show the gamma-ray induced charge distribution as a function of gamma-ray doses. Using the developed model, we have also calculated the corresponding threshold voltage shifts of MOS transistors. These results were compared with the experimentally determined threshold voltage shift of MOS transistors with different voltages applied during irradiation vs. gamma radiation doses. Satisfactory agreements were obtained.

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The Use of C-V Techniques To Investigate Instability Mechanisms in M-I-S Structures

MRS Proceedings ◽

10.1557/proc-716-b11.4 ◽

2002 ◽

Vol 716 ◽

Author(s):

S. Paul ◽

W.I Milne ◽

J. Robertson

Keyword(s):

Threshold Voltage ◽

Chemical Vapour ◽

Charge Trapping ◽

Gate Insulator ◽

Gate Bias ◽

Major Drawback ◽

Threshold Voltage Shift ◽

Voltage Shift ◽

Chemical Vapour Deposition Technique ◽

Mis Structures

AbstractIn the field of flat panel displays, the current leading technology is the Active Matrix liquid Crystal Display; this uses a-Si:H based thin film transistors (TFTs) as the switching element in each pixel. However, under gate bias a-Si:H TFTs suffer from instability, as is evidenced by a shift in the gate threshold voltage. The shift in the gate threshold voltage is generally measured from the gate transfer characteristics, after subjecting the TFT to prolonged gate bias. However, a major drawback of this measurement method is that it cannot distinguish whether the shift is caused by the change in the midgap states in the a-Si:H channel or by charge trapping in the gate insulator. In view of this, we have developed a capacitance-voltage (C-V) method to measure the shift in threshold voltage. We employ Metal-Insulator-Semiconductor (MIS) structures to investigate the threshold voltage shift as they are simpler to fabricate than TFTs. We have investigated a large of number Metal/a-Si:H/Si3N4/Si+n structures using our C-V technique. From, the C-V data for the MIS structures, we have found that the relationship between the thermal energy and threshold voltage shift is similar to that reported by Wehrspohn et. al in a-Si:H TFTs (J Appl. Phys, 144, 87, 2000). The a-Si:H and Si3N4 layers were grown using the radiofrequency plasma-enhanced chemical vapour deposition technique.

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Abnormal Threshold Voltage Shifts in P-Channel Low-Temperature Polycrystalline Silicon Thin Film Transistors Under Negative Bias Temperature Stress

Journal of Nanoscience and Nanotechnology ◽

10.1166/jnn.2015.11167 ◽

2015 ◽

Vol 15 (10) ◽

pp. 7555-7558 ◽

Cited By ~ 1

Author(s):

Sang Sub Kim ◽

Pyung Ho Choi ◽

Do Hyun Baek ◽

Jae Hyeong Lee ◽

Byoung Deog Choi

Keyword(s):

Thin Film ◽

Low Temperature ◽

Threshold Voltage ◽

Thin Film Transistors ◽

Polycrystalline Silicon ◽

Charge Trapping ◽

Trap States ◽

Silicon Thin Film ◽

Threshold Voltage Shift ◽

Voltage Shift

In this research, we have investigated the instability of P-channel low-temperature polycrystalline silicon (poly-Si) thin-film transistors (LTPS TFTs) with double-layer SiO2/SiNX dielectrics. A negative gate bias temperature instability (NBTI) stress was applied and a turn-around behavior phenomenon was observed in the Threshold Voltage Shift (Vth). A positive threshold voltage shift occurs in the first stage, resulting from the negative charge trapping at the SiNX/SiO2 dielectric interface being dominant over the positive charge trapping at dielectric/Poly-Si interface. Following a stress time of 7000 s, the Vth switches to the negative voltage direction, which is “turn-around” behavior. In the second stage, the Vth moves from −1.63 V to −2 V, overwhelming the NBTI effect that results in the trapping of positive charges at the dielectric/Poly-Si interface states and generating grain-boundary trap states and oxide traps.

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