Improvement of Capacitance Equivalent Thickness, Leakage Current, and Interfacial State Density Based on Crystallized High-KDielectrics/Nitrided Buffer Layer Gate Stacks

ABSTRACTThe ability of controlling the growth and interfaces of ultrathin dielectric films on Si and compound semiconductors by ultrahigh vacuum physical vapor deposition has led to comprehensive studies of gate stacks employing the high κ gate oxide Ga2O3(Gd2O3), and the rare earth oxides Gd2O3 and Y2O3. The epitaxy and the interfaces of Gd2O3 on GaAs, GaN, and Si were characterized with atomic precision, and show strong tendency to conform to the underlying substrate, thus providing insight into the fundamental mechanism for low interfacial state density and effective passivation of GaAs and GaN surfaces. These Gd2O3 and Y2O3 gate stacks of abrupt interfaces and controlled microstructures were employed as a model system to elucidate critical issues of materials integration in CMOS scaling.

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Chemical Bath Deposition of Cd1−xZnxS as Buffer Layer in CIGS Solar Cell

Distributed Generation & Alternative Energy Journal ◽

10.13052/dgaej2156-3306.37216 ◽

2021 ◽

Author(s):

Yuming Xue ◽

Xinyu Wang ◽

Liming Zhang ◽

Shipeng Zhang ◽

Lang Wang ◽

...

Keyword(s):

Thin Films ◽

Solar Cell ◽

Buffer Layer ◽

Chemical Bath Deposition ◽

Deposition Rate ◽

Lattice Mismatch ◽

Solution Concentration ◽

State Density ◽

Cubic Phase ◽

Cigs Solar Cell

Cd1-xZnxS thin films were deposited on glass substrates by chemical bath deposition (CBD). The effect of ZnSO4 solution concentration on the properties of the thin films was analyzed. The concentration of ZnSO4 solution affects the deposition rate of Cd1-xZnxS thin films. When the deposition rate is low, Cd1-xZnxS cubic crystal phase is formed. The surface morphology of hexagonal Cd1-xZnxS thin films is denser than that of cubic phase, the lattice mismatch rate of cubic phase Cd1-xZnxS thin films and CIGS is lower, only 0.56%, the interfacial state density is lower. SCAPS software was used to simulate the performance of the buffer layer, and the conversion efficiency of the cubic phase Cd1-xZnxS buffer layer in CIGS Solar Cell was up to 23.50%. Based on the EDS results, the function relationship between the contents of Zn2+ and Cd2+ in the films and the band gap content was deduced.

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20 kV 4H-SiC N-IGBTs

Materials Science Forum ◽

10.4028/www.scientific.net/msf.778-780.1030 ◽

2014 ◽

Vol 778-780 ◽

pp. 1030-1033 ◽

Cited By ~ 17

Author(s):

Sei Hyung Ryu ◽

Craig Capell ◽

Charlotte Jonas ◽

Michael J. O'Loughlin ◽

Jack Clayton ◽

...

Keyword(s):

Buffer Layer ◽

Leakage Current ◽

Supply Voltage ◽

Boost Converter ◽

Power Switching ◽

Switching Device ◽

Blocking Voltage ◽

Off Time ◽

Drift Layer ◽

Stop Buffer

A 1 cm x 1 cm 4H-SiC N-IGBT exhibited a blocking voltage of 20.7 kV with a leakage current of 140 μA, which represents the highest blocking voltage reported from a semiconductor power switching device to this date. The device used a 160 μm thick drift layer and a 1 μm thick Field-Stop buffer layer, and showed a VF of 6.4 V at an IC of 20 A, and a differential Ron,sp of 28 mΩ-cm2. Switching measurements with a supply voltage of 8 kV were performed, and a turn-off time of 1.1 μs and turn-off losses of 10.9 mJ were measured at 25°C, for a 8.4 mm x 8.4 mm device with 140 μm drift layer and 2 μm F-S buffer layer. The turn-off losses were reduced by approximately 50% by using a 5 μm F-S buffer layer. A 55 kW, 1.7 kV to 7 kV boost converter operating at 5 kHz was demonstrated using the 4H-SiC N-IGBT, and an efficiency value of 97.8% was reported.

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Improved Reverse Leakage Current in GaInN-Based LEDs With a Sputtered AlN Buffer Layer

IEEE Photonics Technology Letters ◽

10.1109/lpt.2019.2952106 ◽

2019 ◽

Vol 31 (24) ◽

pp. 1971-1974

Author(s):

Dong-Pyo Han ◽

Seiji Ishimoto ◽

Ryoya Mano ◽

Weifang Lu ◽

Motoaki Iwaya ◽

...

Keyword(s):

Buffer Layer ◽

Leakage Current ◽

Reverse Leakage Current ◽

Aln Buffer

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Impact of byproducts formed on a 4H–SiC surface on interface state density of Al2O3/4H–SiC(0001) gate stacks

Applied Physics Letters ◽

10.1063/1.5143574 ◽

2020 ◽

Vol 116 (22) ◽

pp. 222104

Author(s):

Takuma Doi ◽

Shigehisa Shibayama ◽

Wakana Takeuchi ◽

Mitsuo Sakashita ◽

Noriyuki Taoka ◽

...

Keyword(s):

Interface State ◽

State Density ◽

Interface State Density ◽

Gate Stacks

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Passivation and interface state density of SiO2/HfO2-based/polycrystalline-Si gate stacks

Applied Physics Letters ◽

10.1063/1.1592639 ◽

2003 ◽

Vol 83 (3) ◽

pp. 533-535 ◽

Cited By ~ 99

Author(s):

R. J. Carter ◽

E. Cartier ◽

A. Kerber ◽

L. Pantisano ◽

T. Schram ◽

...

Keyword(s):

Interface State ◽

State Density ◽

Interface State Density ◽

Gate Stacks

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Growth of 4H-SiC Epitaxial Layer through Optimization of Buffer Layer

Materials Science Forum ◽

10.4028/www.scientific.net/msf.924.84 ◽

2018 ◽

Vol 924 ◽

pp. 84-87 ◽

Cited By ~ 3

Author(s):

Nicolò Piluso ◽

Andrea Severino ◽

Ruggero Anzalone ◽

Maria Ausilia di Stefano ◽

Enzo Fontana ◽

...

Keyword(s):

Buffer Layer ◽

Leakage Current ◽

Breakdown Voltage ◽

Epitaxial Layer ◽

Electrical Parameters ◽

Crystallographic Defects

In this work the deposition of buffer layer has been studied in order to increase the quality of the epitaxial layer and improve the performance of device. The comparison between two different thicknesses of buffer layer reveals a decrease of crystallographic defects and an improvement of electrical parameters of MOSFET device as leakage current and breakdown voltage.

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