Design of MOS-translinear Multiplier/Dividers in Analog VLSI
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A general framework for designing current-mode CMOS analog multiplier/divider circuits based on the cascade connection of a geometric-mean circuit and a squarer/divider is presented. It is shown how both building blocks can be readily obtained from a generic second-order MOS translinear loop. Various implementations are proposed, featuring simplicity, favorable precision and wide dynamic range. They can be successfully employed in a wide range of analog VLSI processing tasks. Experimental results of two versions, based on stacked and folded MOS-translinear loops and fabricated in a 2.4-μm CMOS process, are provided in order to verify the correctness of the proposed approach.
1986 ◽
Vol 21
(6)
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pp. 1120-1122
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2002 ◽
Vol 56
(1)
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pp. 55-60
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2017 ◽
Vol 118
(1)
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pp. 507-519
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2021 ◽
Keyword(s):
2017 ◽
pp. 116-120
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