scholarly journals Toward High Throughput Core-CBCM CMOS Capacitive Sensors for Life Science Applications: A Novel Current-Mode for High Dynamic Range Circuitry

Sensors ◽  
2018 ◽  
Vol 18 (10) ◽  
pp. 3370 ◽  
Author(s):  
Saghi Forouhi ◽  
Rasoul Dehghani ◽  
Ebrahim Ghafar-Zadeh
Keyword(s):  
High Performance ◽  
Life Science ◽  
Dynamic Range ◽  
Current Mode ◽  
Capacitive Sensor ◽  
Oxide Semiconductor ◽  
Capacitance Measurement ◽  
Biological Research ◽  
Cmos Process ◽  
Capacitive Sensors

This paper proposes a novel charge-based Complementary Metal Oxide Semiconductor (CMOS) capacitive sensor for life science applications. Charge-based capacitance measurement (CBCM) has significantly attracted the attention of researchers for the design and implementation of high-precision CMOS capacitive biosensors. A conventional core-CBCM capacitive sensor consists of a capacitance-to-voltage converter (CVC), followed by a voltage-to-digital converter. In spite of their high accuracy and low complexity, their input dynamic range (IDR) limits the advantages of core-CBCM capacitive sensors for most biological applications, including cellular monitoring. In this paper, after a brief review of core-CBCM capacitive sensors, we address this challenge by proposing a new current-mode core-CBCM design. In this design, we combine CBCM and current-controlled oscillator (CCO) structures to improve the IDR of the capacitive readout circuit. Using a 0.18 μm CMOS process, we demonstrate and discuss the Cadence simulation results to demonstrate the high performance of the proposed circuitry. Based on these results, the proposed circuit offers an IDR ranging from 873 aF to 70 fF with a resolution of about 10 aF. This CMOS capacitive sensor with such a wide IDR can be employed for monitoring cellular and molecular activities that are suitable for biological research and clinical purposes.

scholarly journals A 4-bit 36 GS/s ADC with 18 GHz Analog Bandwidth in 40 nm CMOS Process

Electronics ◽  
2020 ◽  
Vol 9 (10) ◽  
pp. 1733
Author(s):  
Hanbo Jia ◽  
Xuan Guo ◽  
Xuqiang Zheng ◽  
Xiaodi Xu ◽  
Danyu Wu ◽  
...  
Keyword(s):  
High Speed ◽  
Dynamic Range ◽  
Complementary Metal Oxide Semiconductor ◽  
Current Mode ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Nyquist Frequency ◽  
Least Significant Bit ◽  
Analog To Digital ◽  
Differential Nonlinearity

This paper presents a 4-bit 36 GS/s analog-to-digital converter (ADC) employing eight time-interleaved (TI) flash sub-ADCs in 40 nm complementary metal-oxide-semiconductor (CMOS) process. A wideband front-end matching circuit based on a peaking inductor is designed to increase the analog input bandwidth to 18 GHz. A novel offset calibration that can achieve quick detection and accurate correction without affecting the speed of the comparator is proposed, guaranteeing the high-speed operation of the ADC. A clock distribution circuit based on CMOS and current mode logic (CML) is implemented in the proposed ADC, which not only maintains the speed and quality of the high-speed clock, but also reduces the overall power consumption. A timing mismatch calibration is integrated into the chip to achieve fast timing mismatch detection of the input signal which is bandlimited to the Nyquist frequency for the complete ADC system. The experimental results show that the differential nonlinearity (DNL) and integral nonlinearity (INL) are −0.28/+0.22 least significant bit (LSB) and −0.19/+0.16 LSB, respectively. The signal-to-noise-and-distortion ratio (SNDR) is above 22.5 dB and the spurious free dynamic range (SFDR) is better than 35 dB at 1.2 GHz. An SFDR above 24.5 dB and an SNDR above 18.6 dB across the entire Nyquist frequency can be achieved. With a die size of 2.96 mm * 1.8 mm, the ADC consumes 780 mW from the 0.9/1.2/1.8 V power supply.

scholarly journals Universal Filter Based on Compact CMOS Structure of VDDDA

Sensors ◽  
2021 ◽  
Vol 21 (5) ◽  
pp. 1683
Author(s):  
Winai Jaikla ◽  
Fabian Khateb ◽  
Tomasz Kulej ◽  
Koson Pitaksuttayaprot
Keyword(s):  
Metal Oxide ◽  
Dynamic Range ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Experimental Results ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Voltage Gain ◽  
Universal Filter ◽  
Mos Transistor

This paper proposes the simulated and experimental results of a universal filter using the voltage differencing differential difference amplifier (VDDDA). Unlike the previous complementary metal oxide semiconductor (CMOS) structures of VDDDA that is present in the literature, the present one is compact and simple, owing to the employment of the multiple-input metal oxide semiconductor (MOS) transistor technique. The presented filter employs two VDDDAs, one resistor and two grounded capacitors, and it offers low-pass: LP, band-pass: BP, band-reject: BR, high-pass: HP and all-pass: AP responses with a unity passband voltage gain. The proposed universal voltage mode filter has high input impedances and low output impedance. The natural frequency and bandwidth are orthogonally controlled by using separated transconductance without affecting the passband voltage gain. For a BP filter, the root mean square (RMS) of the equivalent output noise is 46 µV, and the third intermodulation distortion (IMD3) is −49.5 dB for an input signal with a peak-to peak of 600 mV, which results in a dynamic range (DR) of 73.2 dB. The filter was designed and simulated in the Cadence environment using a 0.18-µm CMOS process from Taiwan semiconductor manufacturing company (TSMC). In addition, the experimental results were obtained by using the available commercial components LM13700 and AD830. The simulation results are in agreement with the experimental one that confirmed the advantages of the filter.

A 20-MHz BW MASH Sigma–Delta Modulator with Mismatch Noise Randomization for Multi-Bit DACs

2019 ◽  
Vol 29 (07) ◽  
pp. 2050108
Author(s):  
Di Li ◽  
Chunlong Fei ◽  
Qidong Zhang ◽  
Yani Li ◽  
Yintang Yang
Keyword(s):  
Dynamic Range ◽  
Sampling Rate ◽  
Oxide Semiconductor ◽  
Quantization Noise ◽  
Cmos Process ◽  
Noise Shaping ◽  
Signal To Noise ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Chip Area

A high-linearity Multi-stAge noise SHaping (MASH) 2–2–2 sigma–delta modulator (SDM) for 20-MHz signal bandwidth (BW) was presented. Multi-bit quantizers were employed in each stage to provide a sufficiently low quantization noise level and thus improve the signal-to-noise ratio (SNR) performance of the modulator. Mismatch noise in the internal multi-bit digital-to-analog converters (DACs) was analyzed in detail, and an alternative randomization scheme based on multi-layer butterfly-type network was proposed to suppress spurious tones in the output spectrum. Fabricated in a 0.18-[Formula: see text]m single–poly 4-metal Complementary Metal Oxide Semiconductor (CMOS) process, the modulator occupied a chip area of 0.45[Formula: see text]mm2, and dissipated a power of 28.8[Formula: see text]mW from a 1.8-V power supply at a sampling rate of 320[Formula: see text]MHz. The measured spurious-free dynamic range (SFDR) was 94[Formula: see text]dB where 17-dB improvement was achieved by applying the randomizers for multi-bit DACs in the first two stages. The peak signal-to-noise and distortion ratio (SNDR) was 76.9[Formula: see text]dB at [Formula: see text]1 dBFS @ 2.5-MHz input, and the figure-of-merit (FOM) was 126[Formula: see text]pJ/conv.

High-Performance Current-Mode Logic Ternary D Flip-Flop Based on Bipolar Complementary Metal Oxide Semiconductor

2021 ◽  
Vol 16 (4) ◽  
pp. 528-533
Author(s):  
Xianghong Zhao ◽  
Longhua Ma ◽  
Hongye Su ◽  
Jieyu Zhao ◽  
Weiming Cai
Keyword(s):  
High Frequency ◽  
High Speed ◽  
High Performance ◽  
Complementary Metal Oxide Semiconductor ◽  
Current Mode ◽  
Oxide Semiconductor ◽  
Logic Function ◽  
Flip Flop ◽  
Current Mode Logic ◽  
Transmission Speed

In this paper, a simple-structured and high-performance current-mode logic (CML) ternary D flip-flop based on BiCMOS is proposed. It combines both advantages of BiCMOS and CML circuits, which is with much more high-speed, strong-drive and anti-interference abilities. Utilizing TSMC 180 nm process, results of simulations carried out by HSPICE illustrate the proposed circuit not only has correct logic function, but also gains improvements of 95.6~98.4% in average D-Q delay and 16.2%~70.4 in PDP compared with advanced ternary D flip-flop. When compared at the same information transmission speed, proposed circuit is more competitive. Furthermore, it can perform up to high frequency of 15 GHz and drive heavier load. All the results prove that proposed circuit is high-performance and very suitable for high-speed and high-frequency applications.

scholarly journals A 1.15 μW 200 kS/s 10-b Monotonic SAR ADC Using Dual On-Chip Calibrations and Accuracy Enhancement Techniques

Sensors ◽  
2018 ◽  
Vol 18 (10) ◽  
pp. 3486
Author(s):  
Jae-Hun Lee ◽  
Dasom Park ◽  
Woojin Cho ◽  
Huu Phan ◽  
Cong Nguyen ◽  
...  
Keyword(s):  
Energy Efficient ◽  
Dynamic Range ◽  
Sampling Error ◽  
Sampling Rate ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Calibration Technique ◽  
Accuracy Enhancement ◽  
On Chip ◽  
Comparator Offset

Herein, we present an energy efficient successive-approximation-register (SAR) analog-to-digital converter (ADC) featuring on-chip dual calibration and various accuracy-enhancement techniques. The dual calibration technique is realized in an energy and area-efficient manner for comparator offset calibration (COC) and digital-to-analog converter (DAC) capacitor mismatch calibration. The calibration of common-mode (CM) dependent comparator offset is performed without using separate circuit blocks by reusing the DAC for generating calibration signals. The calibration of the DAC mismatch is efficiently performed by reusing the comparator for delay-based mismatch detection. For accuracy enhancement, we propose new circuit techniques for a comparator, a sampling switch, and a DAC capacitor. An improved dynamic latched comparator is proposed with kick-back suppression and CM dependent offset calibration. An accuracy-enhanced bootstrap sampling switch suppresses the leakage-induced error <180 μV and the sampling error <150 μV. The energy-efficient monotonic switching technique is effectively combined with thermometer coding, which reduces the settling error in the DAC. The ADC is realized using a 0.18 μm complementary metal–oxide–semiconductor (CMOS) process in an area of 0.28 mm2. At the sampling rate fS = 9 kS/s, the proposed ADC achieves a signal-to-noise and distortion ratio (SNDR) of 55.5 dB and a spurious-free dynamic range (SFDR) of 70.6 dB. The proposed dual calibration technique improves the SFDR by 12.7 dB. Consuming 1.15 μW at fS = 200 kS/s, the ADC achieves an SNDR of 55.9 dB and an SFDR of 60.3 dB with a figure-of-merit of 11.4 fJ/conversion-step.

scholarly journals A Stacked Back Side-Illuminated Voltage Domain Global Shutter CMOS Image Sensor with a 4.0 μm Multiple Gain Readout Pixel

Sensors ◽  
2020 ◽  
Vol 20 (2) ◽  
pp. 486
Author(s):  
Ken Miyauchi ◽  
Kazuya Mori ◽  
Toshinori Otaka ◽  
Toshiyuki Isozaki ◽  
Naoto Yasuda ◽  
...  
Keyword(s):  
Dynamic Range ◽  
High Sensitivity ◽  
Cmos Image Sensor ◽  
Light Sensitivity ◽  
Image Sensor ◽  
Motion Artifacts ◽  
Oxide Semiconductor ◽  
Storage Capacitor ◽  
Cmos Process ◽  
Back Side

A backside-illuminated complementary metal-oxide-semiconductor (CMOS) image sensor with 4.0 μm voltage domain global shutter (GS) pixels has been fabricated in a 45 nm/65 nm stacked CMOS process as a proof-of-concept vehicle. The pixel components for the photon-to-voltage conversion are formed on the top substrate (the first layer). Each voltage signal from the first layer pixel is stored in the sample-and-hold capacitors on the bottom substrate (the second layer) via micro-bump interconnection to achieve a voltage domain GS function. The two sets of voltage domain storage capacitor per pixel enable a multiple gain readout to realize single exposure high dynamic range (SEHDR) in the GS operation. As a result, an 80dB SEHDR GS operation without rolling shutter distortions and motion artifacts has been achieved. Additionally, less than −140dB parasitic light sensitivity, small noise floor, high sensitivity and good angular response have been achieved.

HIGH-FREQUENCY LINEAR MULTIPLE-OUTPUT CMOS TRANSCONDUCTANCE AMPLIFIER FOR CURRENT-MODE FILTERS

2006 ◽  
Vol 15 (05) ◽  
pp. 701-717 ◽  
Author(s):  
HSIAO WEI SU ◽  
YICHUANG SUN
Keyword(s):  
High Frequency ◽  
Dynamic Range ◽  
Low Voltage ◽  
Filter Design ◽  
Current Mode ◽  
Cmos Process ◽  
Common Mode ◽  
Differential Input ◽  
Transconductance Amplifier ◽  
Linear Differential

A high-frequency highly linear tunable CMOS multiple-output operational transconductance amplifier (MO-OTA) for fully balanced current-mode OTA and capacitor (OTA-C) filters is presented. The MO-OTA is based on the cross-coupled pairs at the input and provides two pairs of differential outputs. A simple common-mode feedback (CMFB) circuit to stabilize the DC output levels of the MO-OTA is also proposed and two such CMFB circuits are used by the MO-OTA. The proposed MO-OTA is suitable for relatively low voltage (2.5 V) applications as its circuit has only two MOS transistors between the supply and ground rails. Simulated in a TSMC 0.25 μm CMOS process using PSpice, the MO-OTA has at least ± 0.3 V linear differential input signal swing with a single 2.5 V power supply and operates up to 1 GHz frequency. The MO-OTA has a THD less than -46 dB for a differential input voltage of 0.9 Vp-p at 10 MHz, dynamic range (DR) at THD = -46 dB is over 50 dB, and power consumption (with the common-mode feedback circuit) is below 8 mW for the whole tuning range. A fully balanced multiple loop feedback current-mode OTA-C filter example using the proposed MO-OTA is presented. This example also shows that the current-mode follow-the-leader-feedback (FLF) structure can achieve good performances for OTA-C filter design.

scholarly journals 0.5 V Fifth-Order Butterworth Low-Pass Filter Using Multiple-Input OTA for ECG Applications

Sensors ◽  
2020 ◽  
Vol 20 (24) ◽  
pp. 7343
Author(s):  
Montree Kumngern ◽  
Nattharinee Aupithak ◽  
Fabian Khateb ◽  
Tomasz Kulej
Keyword(s):  
Power Consumption ◽  
Dynamic Range ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Subthreshold Region ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Multiple Input ◽  
Low Pass ◽  
Fifth Order

This paper presents a 0.5 V fifth-order Butterworth low-pass filter based on multiple-input operational transconductance amplifiers (OTA). The filter is designed for electrocardiogram (ECG) acquisition systems and operates in the subthreshold region with nano-watt power consumption. The used multiple-input technique simplifies the overall structure of the OTA and reduces the number of active elements needed to realize the filter. The filter was designed and simulated in the Cadence environment using a 0.18 µm Complementary Metal Oxide Semiconductor (CMOS) process from Taiwan Semiconductor Manufacturing Company (TSMC). Simulation results show that the filter has a bandwidth of 250 Hz, a power consumption of 34.65 nW, a dynamic range of 63.24 dB, attaining a figure-of-merit of 0.0191 pJ. The corner (process, voltage, temperature: PVT) and Monte Carlo (MC) analyses are included to prove the robustness of the filter.

scholarly journals Tunable seesaw-like 3D capacitive sensor for force and acceleration sensing

2021 ◽  
Vol 5 (1) ◽  
Author(s):  
Jilong Ye ◽  
Fan Zhang ◽  
Zhangming Shen ◽  
Shunze Cao ◽  
Tianqi Jin ◽  
...  
Keyword(s):  
High Performance ◽  
Low Cost ◽  
High Sensitivity ◽  
Capacitive Sensor ◽  
Mechanical Tests ◽  
Structure Design ◽  
Capacitive Sensors ◽  
Wearable Electronics ◽  
Potential Applications ◽  
The Stability

AbstractTo address the resource-competing issue between high sensitivity and wide working range for a stand-alone sensor, development of capacitive sensors with an adjustable gap between two electrodes has been of growing interest. While several approaches have been developed to fabricate tunable capacitive sensors, it remains challenging to achieve, simultaneously, a broad range of tunable sensitivity and working range in a single device. In this work, a 3D capacitive sensor with a seesaw-like shape is designed and fabricated by the controlled compressive buckling assembly, which leverages the mechanically tunable configuration to achieve high-precision force sensing (resolution ~5.22 nN) and unprecedented adjustment range (by ~33 times) of sensitivity. The mechanical tests under different loading conditions demonstrate the stability and reliability of capacitive sensors. Incorporation of an asymmetric seesaw-like structure design in the capacitive sensor allows the acceleration measurement with a tunable sensitivity. These results suggest simple and low-cost routes to high-performance, tunable 3D capacitive sensors, with diverse potential applications in wearable electronics and biomedical devices.

An Ultra-Low-Voltage Low-Power Current-Mode True RMS-to-DC Converter

2016 ◽  
Vol 25 (06) ◽  
pp. 1650066 ◽  
Author(s):  
Pantre Kompitaya ◽  
Khanittha Kaewdang
Keyword(s):  
Integrated Circuits ◽  
Low Power ◽  
High Performance ◽  
Dynamic Range ◽  
Low Voltage ◽  
Supply Voltage ◽  
Circuit Complexity ◽  
Current Mode ◽  
Cmos Technology ◽  
Low Supply Voltage

A current-mode CMOS true RMS-to-DC (RMS: root-mean-square) converter with very low voltage and low power is proposed in this paper. The design techniques are based on the implicit computation and translinear principle by using CMOS transistors that operate in the weak inversion region. The circuit can operate for two-quadrant input current with wide input dynamic range (0.4–500[Formula: see text]nA) with an error of less than 1%. Furthermore, its features are very low supply voltage (0.8[Formula: see text]V), very low power consumption ([Formula: see text]0.2[Formula: see text]nW) and low circuit complexity that is suitable for integrated circuits (ICs). The proposed circuit is designed using standard 0.18[Formula: see text][Formula: see text]m CMOS technology and the HSPICE simulation results show the high performance of the circuit and confirm the validity of the proposed design technique.

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