Low Phase Noise and High Conversion Gain Oscillator Mixer Constructed with a 0.18-μm CMOS Technology

This paper presents a compact down-conversion oscillator mixer fabricated with a 0.18-μm CMOS technology. The oscillator mixer consists of a conventional nMOS differential coupled oscillator, a switch stage, and a pMOS cross-coupled pair which is used to release the design constraint between the conversion gain and the start-up condition. Since the switch stage and the pMOS cross-coupled pair are stacked on the nMOS differential oscillator, the bias currents of the switch stage and the pMOS cross-coupled pair can be entirely reused, so as to reduce the power dissipation. The experimental results show a conversion gain of 6.5 dB at 2.1 GHz associated with a single-sideband (SSB) noise figure of below 13 dB. The oscillator mixer also exhibits a tuning range of 184 MHz and a phase noise of −116 dBc/Hz at 1-MHz offset from the LO frequency of 6.8 GHz, and it consumes 11 mA from 1.8 V bias voltage.

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Innovative Strategy for Mixer Design Optimization Based on gm/ID Methodology

Electronics ◽

10.3390/electronics8090954 ◽

2019 ◽

Vol 8 (9) ◽

pp. 954 ◽

Cited By ~ 3

Author(s):

Giovanni Piccinni ◽

Claudio Talarico ◽

Gianfranco Avitabile ◽

Giuseppe Coviello

Keyword(s):

Power Dissipation ◽

Figure Of Merit ◽

Noise Figure ◽

Cmos Technology ◽

Third Order ◽

Innovative Strategy ◽

The Core ◽

Mixer Design ◽

Down Conversion ◽

A Current

This work introduces a process to optimize the design of a down-conversion mixer using an innovative strategy based on the gm/ID methodology. The proposed process relies on a set of technology-oriented lookup tables to optimize the trade-off between gain, power dissipation, noise, and distortion. The design is implemented using a 0.13 μm CMOS technology, and to the best of our knowledge, it possesses the best (post-layout simulation) figure of merit (FOM) among the works presented in literature. The FOM is defined as the product of gain and third-order intercept divided the product between average noise figure and power dissipation. Finally, the core of the mixer takes only 31 µm by 28 µm and it draws a current of 1 mA from the 1.5 V DC supply.

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0.5-7.5 GHZ LOW-POWER, INDUCTORLESS CURRENT FOLDED MIXER IN 0.18-μM CMOS FOR BROADBAND APPLICATIONS

International Journal of Electronics and Electical Engineering ◽

10.47893/ijeee.2013.1079 ◽

2013 ◽

pp. 112-116

Author(s):

ZAHRA GHANE FASHTALI ◽

MAHROKH MAGHSOODI ◽

REZA EBRAHIMI ATANI ◽

MEHRGAN MAHDAVI

Keyword(s):

Low Power ◽

Power Dissipation ◽

Noise Figure ◽

Cmos Process ◽

Conversion Gain ◽

Fully Differential ◽

Dc Power ◽

Maximum Conversion ◽

Cell Topology ◽

Down Conversion

A fully differential low-power down-conversion mixer using a TSMC 0.18-μm CMOS process is presented in this paper. The proposed mixer is based on a folded double-balanced Gilbert cell topology that enhances conversion gain and reduces power dissipation. Though, this mixer is designed for 5.8 GHz ISM band applications, but at 0.5-7.5 GHz, the proposed mixer exhibits a maximum conversion gain of 12dB, maximum IIP3 of -2.5 dBm, maximum input 1-dB compression point of -13 dBm, the minimum DSB noise figure of 9.2 dB and a dc power consumption of 2.52 mW at 1.8 V power supply. Also, this circuit architecture increases port-to-port isolations to above 140 dB. Moreover this mixer is suitable for broadband applications.

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A Low-Power, High-Gain, and Low-Noise 802.11a Down-Conversion Mixer in 0.35-μm SiGe Bi-CMOS Technology

Journal of Circuits System and Computers ◽

10.1142/s0218126617501341 ◽

2017 ◽

Vol 26 (09) ◽

pp. 1750134 ◽

Cited By ~ 1

Author(s):

Jun-Da Chen ◽

Song-Hao Wang

Keyword(s):

Low Power ◽

Noise Figure ◽

Supply Voltage ◽

Cmos Technology ◽

High Gain ◽

Low Noise ◽

Cmos Process ◽

Conversion Gain ◽

Dc Power ◽

Down Conversion

The paper presents a novel 5.15[Formula: see text]GHz–5.825[Formula: see text]GHz SiGe Bi-CMOS down-conversion mixer for WLAN 802.11a receiver. The architecture used is based on Gilbert cell mixer, the combination of MOS transistors and HBT BJT transistor device characteristics. The hetero-junction bipolar transistor (HBT) topology is adopted at the transconductance stage to improve power gain and reduce noise factor, and the LO series-parallel CMOS switch topology will be applied to reduce supply voltage and dc power at the switching stage. This mixer is implemented in TSMC 0.35-[Formula: see text]m SiGe Bi-CMOS process, and the chip size including the test pads is 1.175*0.843[Formula: see text]mm2. The main advantages for the proposed mixer are high conversion gain, a moderate linearity, low noise figure, and low power. The post-simulation results achieved are as follows: 14[Formula: see text]dB power conversion gain, [Formula: see text]6[Formula: see text]dBm input third-order intercept point (IIP3), 6.85[Formula: see text]dB double side band (DSB) noise figure. The total mixer current is about 1.54[Formula: see text]mA from 1.4[Formula: see text]V supply voltage including output buffer. The total dc power consumption is 2.15[Formula: see text]mW.

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