The Integration on Electrical Control Systems Based on Optimized Method

2012 ◽  
Vol 490-495 ◽  
pp. 2604-2608
Author(s):  
Ai Rong Zhang
Keyword(s):  
Integrated Circuit ◽  
Large Scale ◽  
Vlsi Design ◽  
Hardware Architecture ◽  
Logic Device ◽  
Integrated Circuit Design ◽  
Large Scale Integration ◽  
Hardware Description ◽  
Description Languages ◽  
Scale Integration

Very large scale integration (VLSI) applications have improved control implementation performance. Indeed, an application specific integrated circuit (ASIC) solution can exploit efficiently specificities of the control algorithms that fixed hardware architecture cannot do. For example, parallel calculation cannot be included in a software solution based on sequential processing. In addition, ASIC can reduce wire and electromagnetic field interference by a fully system on a chip (SoC) integration. However, there are still two main drawbacks to an integrated circuit solution: design complexity and reuse difficulty. This is true even with programmable logic device (PLD) solutions. Conception aid developer (CAD) combined with hardware description languages (HDL) and VLSI design methodology have accelerated conception and reuse. Nevertheless, the main problem of integrated circuit design is to define the hardware architecture; this is particularly true for heterogeneous algorithm structures such as electrical controls.

scholarly journals Gesture Recognition Using Neural Networks Based on HW/SW Cosimulation Platform

2013 ◽  
Vol 2013 ◽  
pp. 1-13 ◽  
Author(s):  
Priyanka Mekala ◽  
Jeffrey Fan ◽  
Wen-Cheng Lai ◽  
Ching-Wen Hsue
Keyword(s):  
American Sign Language ◽  
Gesture Recognition ◽  
Large Scale ◽  
Vlsi Design ◽  
Field Programmable ◽  
Large Scale Integration ◽  
Neural Network Algorithm ◽  
Hardware Description ◽  
And Performance ◽  
Scale Integration

Hardware/software (HW/SW) cosimulation integrates software simulation and hardware simulation simultaneously. Usually, HW/SW co-simulation platform is used to ease debugging and verification for very large-scale integration (VLSI) design. To accelerate the computation of the gesture recognition technique, an HW/SW implementation using field programmable gate array (FPGA) technology is presented in this paper. The major contributions of this work are: (1) a novel design of memory controller in the Verilog Hardware Description Language (Verilog HDL) to reduce memory consumption and load on the processor. (2) The testing part of the neural network algorithm is being hardwired to improve the speed and performance. The American Sign Language gesture recognition is chosen to verify the performance of the approach. Several experiments were carried out on four databases of the gestures (alphabet signs A to Z). (3) The major benefit of this design is that it takes only few milliseconds to recognize the hand gesture which makes it computationally more efficient.

Behavior Models of Voltage Differencing Inverting Buffered Amplifier and Applications in Circuit Analysis

2019 ◽  
Vol 12 (4) ◽  
pp. 298-303
Author(s):  
YongAn LI
Keyword(s):  
Large Scale ◽  
Vlsi Design ◽  
Circuit Analysis ◽  
Second Order ◽  
Very Large Scale Integration ◽  
Behavioral Models ◽  
Order Filter ◽  
Large Scale Integration ◽  
Scale Integration ◽  
Behavior Models

Background: The symbolic nodal analysis acts as a pivotal part of the very large scale integration (VLSI) design. Methods: In this work, based on the terminal relations for the pathological elements and the voltage differencing inverting buffered amplifier (VDIBA), twelve alternative pathological models for the VDIBA are presented. Moreover, the proposed models are applied to the VDIBA-based second-order filter and oscillator so as to simplify the circuit analysis. Results: The result shows that the behavioral models for the VDIBA are systematic, effective and powerful in the symbolic nodal circuit analysis.</P>

scholarly journals Vlsi Interconnection Modelling Using a Finite Element Approach

1995 ◽  
Vol 18 (3) ◽  
pp. 179-202
Author(s):  
Umesh Kumar
Keyword(s):  
Integrated Circuit ◽  
Large Scale ◽  
Low Complexity ◽  
Stratified Medium ◽  
Base Function ◽  
Large Scale Integration ◽  
Element Approach ◽  
Scale Integration ◽  
High Degree ◽  
Important Shift

In the last decade, an important shift has taken place in the design of hardware with the advent of smaller and denser integrated circuit packages. Analysis techniques are required to ensure the proper electrical functioning of this hardware. An efficient method is presented to model the parasitic capacitance of VLSI (very large scale integration) interconnections. It is valid for conductors in a stratified medium, which is considered to be a good approximation for theSi−SiO2system of which present day ICs are made. The model approximates the charge density on the conductors as a continuous function on a web of edges. Each base function in the approximation has the form of a “spider” of edges. Here the method used [1] has very low complexity, as compared to other models used previously [2], and achieves a high degree of precision within the range of validity of the stratified medium.

scholarly journals Unbalanced-Tests to the Improvement of Yield and Quality

Electronics ◽  
2021 ◽  
Vol 10 (23) ◽  
pp. 3032
Author(s):  
Chung-Huang Yeh ◽  
Jwu-E Chen
Keyword(s):  
Integrated Circuit ◽  
Large Scale ◽  
Manufacturing Industry ◽  
Product Distribution ◽  
Test Method ◽  
Distribution Model ◽  
Threshold Test ◽  
Yield And Quality ◽  
Large Scale Integration ◽  
Scale Integration

An integrated-circuit testing model (DITM) is used to describe various factors that affect test yield during a test process. We used a probability distribution model to evaluate test yield and quality and introduced a threshold test and a guardband test. As a result of the development speed of the semiconductor manufacturing industry in the future being unpredictable, we use electrical properties of existing products and the current manufacturing technology to estimate future product-distribution trends. In the development of very-large-scale integration (VLSI) testing, the progress of testing technology is very slow. To improve product testing yield and quality, we change the test method and propose an unbalanced-test method, leading to improvements in test results. The calculation using our proposed model and data estimated by the product published by the IEEE International Roadmap for Devices and Systems (IRDS, 2017) proves that the proposed unbalanced-test method can greatly improve test yield and quality and achieve the goal of high-quality, near-zero-defect products.

scholarly journals PERANCANGAN MULTIPLIER SEKUENSIAL 8-BIT DENGAN TEKNOLOGI 180NM MENGGUNAKAN PERANGKAT LUNAK ELECTRIC

TRANSIENT ◽  
2017 ◽  
Vol 6 (3) ◽  
pp. 476
Author(s):  
Brama Yoga Satria ◽  
Munawar Agus Riyadi ◽  
Muhammad Arfan
Keyword(s):  
Integrated Circuit ◽  
Large Scale ◽  
Very Large Scale Integration ◽  
Shift Register ◽  
Large Scale Integration ◽  
Scale Integration ◽  
Logic Unit

Very Large Scale Integration (VLSI) merupakan proses dari pembuatan sirkuit terpadu atau Integrated Circuit (IC) dengan cara menggabungkan ribuan rangkaian berbasis transistor ke dalam sebuah chip atau prosesor. Dengan adanya VLSI, ukuran dari devais elektronik berbasis transistor dapat dimampatkan agar menghemat area, biaya produksi, dan efek parasitik. Prosesor terdiri dari beberapa blok utama sebagai penunjang kerjanya, salah satu blok yang paling penting yaitu Arithmatic  Logic Unit (ALU). Salah satu contoh dari ALU sendiri yaitu adalah multiplier. Multiplier sangat penting untuk banyak dasar proses dari sebuah prosesor. Tujuan dari penelitian ini adalah merancang sebuah multiplier sekuensial 8-bit dengan teknologi 180nm. Multiplier dirancang dengan menggabungkan blok-blok pembangun seperti blok counter, adder, shift register, dan lain-lainnya. Penelitian ini menggunakan perangkat lunak electric untuk mendesain layout dan perangkat lunak LT-Spice untuk menguji fungsional, delay, dan kinerja dari hasil ekstraksi layout. Hasil perancangan ini secara fungsional telah berjalan dengan baik. Multiplier yang dirancang memiliki layout sebesar 3.725.150 lambda2 dengan nilai delay sebesar 4,428ns. Selain itu, frekuensi maksimum yang digunakan untuk mendapatkan hasil yang benar dari multiplier sekuensial 8-bit yaitu 50MHz.

scholarly journals A HARDWARE IMPLEMENTATION OF PUNGURED CONVOLUTIONAL CODES TO COMPLETE A VITERBI DECODER CORE

2005 ◽  
Vol 3 (02) ◽  
Author(s):  
E. Garda ◽  
M. Guzmán ◽  
D. Torres
Keyword(s):  
Large Scale ◽  
Convolutional Codes ◽  
Viterbi Decoder ◽  
Single Chip ◽  
Description Language ◽  
Large Scale Integration ◽  
Constraint Length ◽  
Hardware Description ◽  
Scale Integration ◽  
Convolutional Encoder

This paper presents a VLSI (Very Large Scale Integration) implementation of high punctured convolutional codes.We present a new circuit architecture that is capable of processing up to 10 convolutional codes rate (n-1)/n withthe constraint length-7 derived by the puncturing technique from the basic rate-1/2. The present circuit wasdesigned in order to complete an existing Viterbi decoder core, adding some extra functionality such as aconvolutional encoder, differential encoder/decoder, punctured convolutional encoder and symbol insertion todepuncture the received data. This extra functionality includes 10 different programmable coding rates without theneed to add additional logic in the system implementation, while other existing coders need it to attain highercoding rates. Therefore, a single chip solution is presented. The design was implemented in VHDL (Very High SpeedIntegrated Circuit Hardware Description Language) synthesized in Synopsys tool, and tested in a FPGA. Functionalverification was done, by means of simulation, to ensure that the circuit implements intended functionality. Suchsimulations were executed using Synopsys and a Sun Ultra Sparc 10 workstation. Different bit error probabilityperformance curves show an agreement between simulated and theoretical values.

An Approach to Reading Machine Design

1978 ◽  
Vol 20 (3) ◽  
pp. 287-293 ◽  
Author(s):  
Jonathan Allen
Keyword(s):  
Integrated Circuit ◽  
Large Scale ◽  
Read Aloud ◽  
Machine Design ◽  
Current Status ◽  
Text To Speech ◽  
Short Term ◽  
Large Scale Integration ◽  
Scale Integration ◽  
Circuit Technology

Within two years, both the required algorithmic competence and the necessary integrated circuit technology will have been developed to a point where practical personal reading machines for the blind will be possible. In this paper, the linguistic and phonetic principles needed to convert optically recognized text to speech are discussed, and it is shown how they mirror the human cognitive ability to read aloud. A perspective on the current status and rate of progress of large scale integration technology is then used to show that economical implementations of even complex text-to-speech algorithms can be realized in the short-term future. Finally, a view of important human factors problems requiring attention is given.

Silicide Applications In Microelectronics

1981 ◽  
Vol 10 ◽  
Author(s):  
Billy L. Crowder
Keyword(s):  
Integrated Circuit ◽  
Polycrystalline Silicon ◽  
Large Scale ◽  
Field Effect Transistor ◽  
Oxide Semiconductor ◽  
Device Structures ◽  
Direct Replacement ◽  
Large Scale Integration ◽  
Effect Transistor ◽  
Scale Integration

ABSTRACTThe advent of very-large-scale integration in microelectronics has been achieved by reduction in lithographic dimensions coupled with a corresponding decrease in vertical dimensions in properly scaled device structures. This development has placed severe demands upon interconnection technology. The practice of using semiconducting regions (diffusions or polycrystalline silicon) for interconnecting devices is no longer viable because of the high resistance associated with such regions (i.e. interconnections do not “scale” properly). One solution to this problem is the use of multilevel metallization, but this requires tens of thousands of small contacts to shallow diffusions. Refractory metals such as titanium are being explored as materials which provide the necessary stable low resistance contacts suitable for integrated circuit applications. Another solution to the problem is to develop a higher conductivity material to replace or supplement polycrystalline silicon. Refractory metal disilicides have been extensively investigated for this application -both as a direct replacement for polycrystalline silicon or in a silicide/polycrystalline silicon composite (polycide). A critical review of the present status in both these areas will be presented. Emphasis will be upon our experience gained in conjunction with the development of a 1 μm silicon gate metal/oxide/ semiconductor field effect transistor technology.

scholarly journals Area Efficient High Speed Vedic Multiplier

2019 ◽  
Vol 8 (9S) ◽  
pp. 302-306
Keyword(s):  
High Speed ◽  
Large Scale ◽  
Arithmetic Operation ◽  
Vlsi Design ◽  
Digital Signal ◽  
Digital Circuit ◽  
Single Chip ◽  
Digital Vlsi ◽  
Large Scale Integration ◽  
Scale Integration

Very large scale integration is a process of integrating hundreds of thousands of transistors or devices into a single chip. VLSI can be categorized into two fields Frontend and Backend. Digital VLSI design falls under the Frontend design. Multiplication is an arithmetic operation important for the Digital Signal Processing (DSP) and for processors. Multiplier is the main hardware block for the digital circuit. More than 70% of the applications in a digital circuit are either addition or multiplication. As these operations dominates most of the execution time so we need fast multipliers. The overall objective of a good multiplier is to have high speed, low power consumption unit, less area. Vedic multipliers are the fast multipliers and occupy less area. They are based on the Vedic mathematics sutra "Urdhava-Triyakbhyam" . The paper contain a high speed multipliers and use of different adder structures.

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