scholarly journals Design and implementation of embedded concurrent laser missile jammer system using FPGA

2019 ◽  
Vol 14 (2) ◽  
pp. 780
Author(s):  
Chin Beng. Lim ◽  
Muataz H. Salih
Keyword(s):  
Operating Frequency ◽  
System Throughput ◽  
Real Time System ◽  
Similar Frequency ◽  
Multiple Data ◽  
Self Testing ◽  
Multiple Missiles ◽  
Field Programmable ◽  
Laser Detector ◽  
Lower Complexity

<span>In real time system, every second takes into count as any extra delay could cause critical consequences. Nowadays, almost every system involving multiple data processing. To handle multiple data at the same time, spatial parallelism is required to enhance system performance and provide multitasking feature. Currently, frequency jamming system only can jam one signal at a time. When it comes to missile jamming, the delaying in processing the frequency could cause serious impact as there will be multiple missiles launched to hit a target. These missiles just need few seconds to hit the target within range. Laser missile jammer is designed, which can jam multiple missiles at a time from different directions. The potentials of Field Programmable Gate Array (FPGA) and spatial parallelism is used in this system, to enhance the performance of the system by increasing operating frequency, system throughput, decreasing system cost, power consumption of the system, and get lower complexity. Quartus II version 14.1 is used in this project as a development CAD tool, the entire system implemented on FPGA DE1-SoC board. Also, other components such as Laser Detector, Laser Transmitter, and monitoring screen is integrated with the board. A signal emulator module was designed, to generate signals for on-board self-testing purpose, this system can detect the frequency of laser missile and create an over-powered signal with similar frequency to jam the missile(s) through diffused plates. All the results are shown on control display. This system had achieved a better throughput and lower complexity in terms of less resource usage (3153 Logic Elements) and high operating frequency (up to 1.6 GHz).</span>

A DSP and FPGA Testbed for Teaching and Research of Wireless Communications

2012 ◽  
Vol 49 (3) ◽  
pp. 232-242 ◽  
Author(s):  
Julian Webber ◽  
Toshihiko Nishimura ◽  
Takeo Ohgane ◽  
Yasutaka Ogawa
Keyword(s):  
Signal Processing ◽  
Real Time ◽  
System Development ◽  
Radio Channel ◽  
Digital Signal ◽  
Lessons Learned ◽  
Real Time System ◽  
Teaching And Research ◽  
Theoretical Concepts ◽  
Field Programmable

This paper describes the teaching and research of signal processing and communications systems that took place during the development of a real-time transceiver and radio channel testbed at Hokkaido University, Japan. Digital signal processing (DSP) concepts were taught and learnt during both the testbed system development and also the results gathering and analysis stages. The performance of a modern multiple antenna communications system is dependent on a number of key parameters, and the student interaction with such a real-time system can assist in the understanding of key but often abstract theoretical concepts. The communications algorithm and architecture overview on a signal processing board containing a Xilinx field programmable gate array (FPGA) and Analog Devices TigerSharc DSP is detailed. The lessons learned and potential uses of the testbed in both teaching and research are also described.

Design and Research of Multiple Data Channels in Solid State Recorder of the Satellite SJ-10

2014 ◽  
Vol 1073-1076 ◽  
pp. 1977-1981
Author(s):  
Qi Song ◽  
Shan Li ◽  
Yan Zhu ◽  
Jun She An
Keyword(s):  
Solid State ◽  
Data Flow ◽  
Storage System ◽  
High Capacity ◽  
Scientific Data ◽  
System Throughput ◽  
Nand Flash ◽  
Multiple Data ◽  
File System Management ◽  
Solid State Recorder

Space borne high-capacity solid state recorder (SSR) is an inevitable chain of the space scientific data acquirement system. It has become a common device in spacecraft gradually. This paper presents the design and accomplishment of the large capacity SSR design based on NAND flash of the satellite SJ-10. The SSR improves its writing speed significantly by applying multi-pipeline writing technique. External SDRAM is used as the channel cache of the multi-channel data flows to increase the cache capacity and system throughput speed. In addition, the EDAC processing, data flow combining and separating can enhance the stability of the storage system as well as the data efficiently. The implementing of multi-channel has also laid the foundation for file system management of the space borne storage data. The simulation of multi-channel data flow is given in this paper.

scholarly journals An FPGA-based Network Firewall with Expandable Rule Description

2018 ◽  
Vol 10 (3) ◽  
pp. 1310
Author(s):  
Raya Kahtan Mohammed ◽  
Yoichiro UENO
Keyword(s):  
System Performance ◽  
High Performance ◽  
System Throughput ◽  
Content Addressable Memory ◽  
Incoming Packet ◽  
Field Programmable ◽  
Software And Hardware ◽  
Firewall System ◽  
The One ◽  
Memory Utilization

<p>With the rapid growth of communications via the Internet, the need for an effective firewall system which has not badly affect the overall network performances has been increased. In this paper, a Field Programmable Gate Array (FPGA) -based firewall system with high performance has been implemented using Network FPGA (NetFPGA) with Xilinx Kintex-7 XC7K325T FPGA. Based on NetFPGA reference router project, a NetFPGA-based firewall system was implemented. The hardware module performs rule matching operation using content addressable memory (CAM) for higher speed data processing. To evaluate system performance, throughput, latency, and memory utilization were measured for different cases using different tools, also the number of rules that an incoming packet is subjected to was varied to get more readings using both software and hardware features. The results showed that the designed firewall system provides better performance than traditional firewalls. System throughput was doubled times of the one with Linux-Iptables firewalls.</p>

scholarly journals Limited Comp Handover Algorithm For LTE-Advanced

2013 ◽  
Vol 2013 ◽  
pp. 1-9 ◽  
Author(s):  
Cheng-Chung Lin ◽  
Kumbesan Sandrasegaran ◽  
Xinning Zhu ◽  
Zhuliang Xu
Keyword(s):  
Base Stations ◽  
System Capacity ◽  
System Throughput ◽  
System Delay ◽  
Coordinated Multipoint ◽  
Multiple Data ◽  
Lte Advanced ◽  
Hard Handover ◽  
Radio Resources ◽  
Handover Algorithm

Coordinated multipoint (CoMP) transmission and reception is the key technique in LTE-Advanced to improve the cell-edge throughput and/or system throughput. Joint processing (JP) in CoMP technology provides multiple data transmission points for each user among multiple cooperated radio base stations. Hard handover mechanism is adopted to be used in LTE-Advanced. Standard hard handover algorithm could not satisfy the concept of JP in CoMP in LTE-A due to the constraint of single connection for each user at any time. While the radio resources in the system are fixed, the more multiple data connections a user has, the more radio resources are used for the extra data connections, thus the lower capacity a system becomes. Therefore a new handover algorithm that not only supports JP in CoMP but also takes system capacity into consideration in LTE-A system is necessary. This paper proposes a new handover algorithm known as Limited CoMP Handover Algorithm to support JP in CoMP and overcome the system capacity issue. System performance of Limited CoMP Handover Algorithm is evaluated and compared with open literature handover algorithm via simulation in this paper. The simulation results show that Limited CoMP Handover Algorithm outperforms open literature handover algorithm by having shorter system delay and less system load whilst maintaining a higher system throughput in a high congested network.

Parallel implementation of aircraft disembarking and emergency evacuation based on cellular automata

2016 ◽  
Vol 31 (2) ◽  
pp. 134-151 ◽  
Author(s):  
Themistoklis Giitsidis ◽  
Nikolaos I Dourvas ◽  
Georgios Ch Sirakoulis
Keyword(s):  
Cellular Automata ◽  
Graphics Processing Unit ◽  
Parallel Implementation ◽  
Emergency Evacuation ◽  
Processing Unit ◽  
Real Time System ◽  
Proposed Model ◽  
Cuda Programming ◽  
Field Programmable ◽  
Emergency Scenarios

In this paper we present a model based on the parallel computational tool of cellular automata (CA) capable of simulating the process of disembarking in a small airplane seat layout, corresponding to Airbus A320/ Boeing 737 layout, in search of ways to make it faster and safer under normal evacuation conditions, as well as emergency scenarios. The proposed model is highly customizable, with the number of exits, the walking speed of passengers, depending on their sex, age and height, and the effects of retrieving and carrying luggage. Additionally, the presence of obstacles in the aisles as well as the emergence of panic being parameters whose values can be varied in order to enlighten the disembarking and emergency evacuation processes are considered in detail. The simulation results were compared to existing aircraft disembarking and evacuation times and indicate the efficacy of the proposed model in investigating and revealing passenger attributes during these processes in all the examined cases. Moreover, we parallelized our code in order to run on a graphics processing unit (GPU) using the CUDA programming language, speeding up the simulation process. Finally, in order to present a fully dynamical anticipative real-time system helpful for decision-making we implemented the proposed CA model in a field programmable gate array (FPGA) device, and recreated the results given by the software simulations in a fraction of the time. We then compared and exported the performance results among a sequential software implementation, the implementation running on a GPU, and a hardware implementation, proving the consequent acceleration that results from the parallel CA implementation in specific hardware.

Transition Test Patterns Generation for BIST Implemented in ASIC and FPGA

2008 ◽  
Vol 144 ◽  
pp. 214-219
Author(s):  
Vidas Abraitis ◽  
Žydrūnas Tamoševičius
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Test Pattern ◽  
Pattern Generation ◽  
Linear Feedback ◽  
Test Sequence ◽  
Self Testing ◽  
Field Programmable ◽  
Application Specific Integrated Circuit ◽  
Transition Delay

Transition delay testing of sequential circuits in a clocked environment is analyzed. There are presented two test pattern generator methods for built in self testing of the circuit implemented as Application Specific Integrated Circuit (ASIC) and Field Programmable Gate Array (FPGA) of Virtex family. Cellular automaton and Linear Feedback Shift Register (LFSR) structures are used for test sequence generation. The circuits are tested as the black boxes under Transition fault model. Experimental results of the test pattern generation methods are presented and analyzed. Results compared with exhaustive test of transition faults for ASICs and programmable integrated circuits with given configuration.

scholarly journals 512 bit-SHA3 design approach and implementation on field programmable gate arrays

2019 ◽  
Vol 8 (3) ◽  
pp. 169
Author(s):  
S. Neelima ◽  
R. Brindha
Keyword(s):  
Field Programmable Gate Arrays ◽  
Fpga Implementation ◽  
Design Approach ◽  
Operating Frequency ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
The One

<p>In this work, the authors consider the newly selected Hash Secure (SHA-3) algorithm on FPGA Gateway. The design is logically optimized for zone efficiency by combining the Rho steps and the one-pass algorithm. Logically recording these three steps registers leads to usage 16% of the logical resources for all implementations. This in turn reduces the latency and increases the maximum operating frequency of the project. It uses only 240 sections and has a frequency of 301.02 MHz compared to the design results with the previous FPGA implementation described in SHA3-512, the design shows the Throughput-Per-Slice (TPS) ratio of 30, 1.</p>

scholarly journals A Parallel Timing Synchronization Structure in Real-Time High Transmission Capacity Wireless Communication Systems

Electronics ◽  
2020 ◽  
Vol 9 (4) ◽  
pp. 652
Author(s):  
Xin Hao ◽  
Changxing Lin ◽  
Qiuyu Wu
Keyword(s):  
Wireless Communication ◽  
Real Time ◽  
Communication Systems ◽  
Digital Signal ◽  
Transmission Capacity ◽  
Timing Synchronization ◽  
Wireless Communication Systems ◽  
Real Time System ◽  
System Clock ◽  
Field Programmable

In the past few years, parallel digital signal processing (PDSP) architectures have been intensively studied to fulfill the growing demand of channel capacity in coherent optical communication systems. However, to our knowledge, real-time timing synchronization in such architectures is until now not implemented on a Field Programmable Gate Array (FPGA). In this article, a parallel timing synchronization architecture is proposed. In the architecture, a parallel First In First Out (FIFO) structure based on an index associated rearranging method, and a dual feedback loop based on the Gardner’s algorithm, are adopted. Taking advantages of the FIFO structure, 67% Look Up Table (LUT) is saved in comparison with earlier results, meanwhile the Numerically Controlled Oscillator (NCO) is efficiently improved to meet the FPGA timing requirements for real-time performance. MATLAB simulations are run to evaluate the Bit Error Rate (BER) deterioration of the architecture. The float- and fixed-point simulation results have shown that, The BER deteriorations are less than 0.5 dB and 1 dB, respectively. Further, the implementation of the architecture on a Xilinx XC7VX485T FPGA chip is achieved. A 20 giga bit per second (Gbps) 16 Quadrature Amplitude Modulation (16QAM) real-time system is achieved at the system clock of 159.524 MHz. This work opens a new pathway to improve the transmission capacity in real-time wireless communication systems.

Configurable Router Design for Dynamically Reconfigurable Systems based on the SoCWire NoC

2013 ◽  
Vol 2 (1) ◽  
pp. 27 ◽  
Author(s):  
Arash Farhadi Beldachi ◽  
Mohammad Hosseinabady ◽  
Jose Luis Nunez-Yanez
Keyword(s):  
Mesh Network ◽  
Core System ◽  
Dynamically Reconfigurable ◽  
Gate Arrays ◽  
Starting Point ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Hardware Configuration ◽  
Lower Complexity ◽  
On Chip

New Field Programmable Gate Arrays (FPGAs) are capable of implementing complete multi-core System-on-Chip (SoC) with the possibility of modifying the hardware configuration at run-time with partial dynamic reconfiguration. The usage of a soft reconfigurable Network-on-Chip (NoC) to connect these cores is investigated in this paper. We have used a standard switch developed with the objective of supporting dynamically reconfigurable FPGAs as the starting point to create a novel configurable router. The configurable router uses distributed routing suitable for regular topologies and can vary the number of local ports and communication ports to build multi dimensional networks (i.e., 2D and 3D) with different topologies. The evaluation results show that the selection of the ideal router is different depending on traffic patterns and design objectives. Overall, the mesh network with a four local ports router offers a higher level of performance with lower complexity compared to the traditional mesh with one local port router.

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