Transition Test Patterns Generation for BIST Implemented in ASIC and FPGA

2008 ◽  
Vol 144 ◽  
pp. 214-219
Author(s):  
Vidas Abraitis ◽  
Žydrūnas Tamoševičius
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Test Pattern ◽  
Pattern Generation ◽  
Linear Feedback ◽  
Test Sequence ◽  
Self Testing ◽  
Field Programmable ◽  
Application Specific Integrated Circuit ◽  
Transition Delay

Transition delay testing of sequential circuits in a clocked environment is analyzed. There are presented two test pattern generator methods for built in self testing of the circuit implemented as Application Specific Integrated Circuit (ASIC) and Field Programmable Gate Array (FPGA) of Virtex family. Cellular automaton and Linear Feedback Shift Register (LFSR) structures are used for test sequence generation. The circuits are tested as the black boxes under Transition fault model. Experimental results of the test pattern generation methods are presented and analyzed. Results compared with exhaustive test of transition faults for ASICs and programmable integrated circuits with given configuration.

An On-Chip Clock Controller for Testing Fault in System on Chip

2013 ◽  
Vol 347-350 ◽  
pp. 724-728
Author(s):  
Wei Lin ◽  
Wen Long Shi
Keyword(s):  
Integrated Circuit ◽  
Test Pattern ◽  
Fault Coverage ◽  
System On Chip ◽  
Pattern Generation ◽  
Integrated Circuit Design ◽  
Scan Test ◽  
High Efficient ◽  
Transition Delay ◽  
On Chip

In this paper, an on-chip clock (OCC) controller with bypass function based on an internal phase locked loop (PLL) is designed to test the faults in system on chip (SOC), such as the transition-delay faults and the stuck-at faults. A clock chain logic which can eliminate the metastable state is realized to generate an enable signal for the OCC controller, and then, the test pattern is generated by the automatic test pattern generation (ATPG) tools. Next, the scan test pattern is simulated by the Synopsys tool and the correctness of the design is verified. The result shows that the design of at-speed scan test in this paper is high efficient for detecting the timing-related defects. Finally, the 89.29 percent transition-delay fault coverage and the 94.50 percent stuck-at fault coverage are achieved, and it is successfully applied to an integrated circuit design.

scholarly journals Soft Computing Approach To Automatic Test Pattern Generation For Sequential Vlsi Circuit

2013 ◽  
pp. 42-47
Author(s):  
Monalisa Mohanty ◽  
S. N. Patnaik
Keyword(s):  
Integrated Circuits ◽  
Test Pattern ◽  
Difficult Problem ◽  
Pattern Generation ◽  
Vlsi Circuits ◽  
Test Sequence ◽  
Test Pattern Generation ◽  
Automatic Test Pattern Generation ◽  
Automatic Test ◽  
Sequence Generation

Due to the constant development in the integrated circuits, the automatic test pattern generation problem become more vital for sequential vlsi circuits in these days. Also testing of integrating circuits and systems has become a difficult problem. In this paper we have discussed the problem of the automatic test sequence generation using particle swarm optimization(PSO) and technique for structure optimization of a deterministic test pattern generator using genetic algorithm(GA).

scholarly journals A P4-Enabled RINA Interior Router for Software-Defined Data Centers

Computers ◽  
2020 ◽  
Vol 9 (3) ◽  
pp. 70
Author(s):  
Carolina Fernández ◽  
Sergio Giménez ◽  
Eduard Grasa ◽  
Steve Bunch
Keyword(s):  
Integrated Circuit ◽  
High Performance ◽  
Data Transfer ◽  
Great Promise ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Application Specific Integrated Circuit ◽  
Networking Technologies ◽  
Application Specific

The lack of high-performance RINA (Recursive InterNetwork Architecture) implementations to date makes it hard to experiment with RINA as an underlay networking fabric solution for different types of networks, and to assess RINA’s benefits in practice on scenarios with high traffic loads. High-performance router implementations typically require dedicated hardware support, such as FPGAs (Field Programmable Gate Arrays) or specialized ASICs (Application Specific Integrated Circuit). With the advance of hardware programmability in recent years, new possibilities unfold to prototype novel networking technologies. In particular, the use of the P4 programming language for programmable ASICs holds great promise for developing a RINA router. This paper details the design and part of the implementation of the first P4-based RINA interior router, which reuses the layer management components of the IRATI Linux-based RINA implementation and implements the data-transfer components using a P4 program. We also describe the configuration and testing of our initial deployment scenarios, using ancillary open-source tools such as the P4 reference test software switch (BMv2) or the P4Runtime API.

A Comprehensive Test Compression Scheme Based on Precomputed Test Sets

2013 ◽  
Vol 756-759 ◽  
pp. 533-541
Author(s):  
Zhi Jian Tian ◽  
Fa Yong Zhao
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Large Scale ◽  
Test Pattern ◽  
Compression Scheme ◽  
Run Length ◽  
Rearrangement Algorithm ◽  
Long Run ◽  
Assignment Strategy ◽  
Run Lengths

To cope with increasingly rigorous challenges that large scale digital integrated circuit testing is confronted with, a comprehensive compression scheme consisting of test-bit rearrangement algorithm, run-length assignment strategy and symmetrical code is proposed. The presented test-bit rearrangement algorithm can fasten dont-care bits, 0s or 1s in every test pattern on one of its end to the greatest extent so as to lengthen end-run blocks and decrease number of short run-lengths. A dynamical dont-care assignment strategy based on run-lengths can be used to specify the remaining dont-care bits after the test-bit rearrangement, which can decrease run-length splitting and maximize length of run-lengths. The symmetrical code benefits from long run-lengths and only uses 2 4-bit short code words to identify end-run blocks almost as long as a test pattern, and hence the utilization ratio of code words can be heightened. The presented experiment results show that the proposed comprehensive scheme can obtain very higher data compression ratios than other compression ones published up to now, especially for large scale digital integrated circuits, and considerably decrease test power dissipations.

scholarly journals Analysis of the Quantization Noise in Discrete Wavelet Transform Filters for Image Processing

Electronics ◽  
2018 ◽  
Vol 7 (8) ◽  
pp. 135 ◽  
Author(s):  
Nikolay Chervyakov ◽  
Pavel Lyakhov ◽  
Dmitry Kaplun ◽  
Denis Butusov ◽  
Nikolay Nagornov
Keyword(s):  
Image Processing ◽  
Wavelet Transform ◽  
Discrete Wavelet Transform ◽  
Integrated Circuit ◽  
Filter Banks ◽  
Signal To Noise Ratio ◽  
Quantization Noise ◽  
Discrete Wavelet ◽  
Field Programmable ◽  
Application Specific Integrated Circuit

In this paper, we analyze the noise quantization effects in coefficients of discrete wavelet transform (DWT) filter banks for image processing. We propose the implementation of the DWT method, making it possible to determine the effective bit-width of the filter banks coefficients at which the quantization noise does not significantly affect the image processing results according to the peak signal-to-noise ratio (PSNR). The dependence between the PSNR of the DWT image quality on the wavelet and the bit-width of the wavelet filter coefficients is analyzed. The formulas for determining the minimal bit-width of the filter coefficients at which the processed image achieves high quality (PSNR ≥ 40 dB) are given. The obtained theoretical results were confirmed through the simulation of DWT for a test image using the calculated bit-width values. All considered algorithms operate with fixed-point numbers, which simplifies their hardware implementation on modern devices: field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), etc.

scholarly journals Sparse Cholesky Factorization on FPGA Using Parameterized Model

2017 ◽  
Vol 2017 ◽  
pp. 1-11
Author(s):  
Yichun Sun ◽  
Hengzhu Liu ◽  
Tong Zhou
Keyword(s):  
Integrated Circuit ◽  
Sparse Matrix ◽  
Fundamental Problem ◽  
Performance Model ◽  
Cholesky Factorization ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Application Specific Integrated Circuit ◽  
Parameterized Model ◽  
And Performance

Cholesky factorization is a fundamental problem in most engineering and science computation applications. When dealing with a large sparse matrix, numerical decomposition consumes the most time. We present a vector architecture to parallelize numerical decomposition of Cholesky factorization. We construct an integrated analytical parameterized performance model to accurately predict the execution times of typical matrices under varying parameters. Our proposed approach is general for accelerator and limited by neither field-programmable gate arrays (FPGAs) nor application-specific integrated circuit. We implement a simplified module in FPGAs to prove the accuracy of the model. The experiments show that, for most cases, the performance differences between the predicted and measured execution are less than 10%. Based on the performance model, we optimize parameters and obtain a balance of resources and performance after analyzing the performance of varied parameter settings. Comparing with the state-of-the-art implementation in CPU and GPU, we find that the performance of the optimal parameters is 2x that of CPU. Our model offers several advantages, particularly in power consumption. It provides guidance for the design of future acceleration components.

scholarly journals Method for improving ripple reduction during phase shedding in multiphase buck converters for SCADA systems

2021 ◽  
Vol 24 (1) ◽  
pp. 29
Author(s):  
Mini P. Varghese ◽  
A. Manjunatha ◽  
T. V. Snehaprabha
Keyword(s):  
Power Supply ◽  
Integrated Circuit ◽  
Buck Converter ◽  
Multiphase System ◽  
Processing Unit ◽  
Central Processing ◽  
Light Load ◽  
Field Programmable ◽  
Ripple Reduction ◽  
Application Specific Integrated Circuit

In the current digital environment, central processing unit (CPUs), field programmable gate array (FPGAs), application-specific integrated circuit (ASICs), as well as peripherals, are growing progressively complex. On motherboards in many areas of computing, from laptops and tablets to servers and Ethernet switches, multiphase phase buck regulators are seen to be more common nowadays, because of the higher power requirements. This study describes a four-stage buck converter with a phase shedding scheme that can be used to power processors in programmable logic controller (PLCs). The proposed power supply is designed to generate a regulated voltage with minimal ripple. Because of the suggested phase shedding method, this power supply also offers better light load efficiency. For this objective, a multiphase system with phase shedding is modeled in MATLAB SIMULINK, and the findings are validated.

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