Capacitorless One-Transistor Dynamic Random-Access Memory Based on Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistor with Si/SiGe Heterojunction and Underlap Structure for Improvement of Sensing Margin and Retention Time

2019 ◽  
Vol 19 (10) ◽  
pp. 6023-6030
Author(s):  
Young Jun Yoon ◽  
Min Su Cho ◽  
Bo Gyeong Kim ◽  
Jae Hwa Seo ◽  
In Man Kang
Keyword(s):  
Retention Time ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Random Access ◽  
Random Access Memory ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Double Gate ◽  
Access Memory ◽  
Effect Transistor

Design and Analysis of Metal-Oxide-Semiconductor Field-Effect Transistor-Based Capacitorless One-Transistor Embedded Dynamic Random-Access Memory with Double-Polysilicon Layer Using Grain Boundary for Hole Storage

2020 ◽  
Vol 20 (11) ◽  
pp. 6596-6602
Author(s):  
Won Douk Jang ◽  
Young Jun Yoon ◽  
Min Su Cho ◽  
Jun Hyeok Jung ◽  
Sang Ho Lee ◽  
...  
Keyword(s):  
Grain Boundary ◽  
Field Effect Transistor ◽  
Random Access ◽  
Random Access Memory ◽  
Metal Oxide Semiconductor ◽  
Dynamic Random Access Memory ◽  
Oxide Semiconductor ◽  
Access Memory ◽  
Polysilicon Layer ◽  
Effect Transistor

In this work, a capacitorless one-transistor embedded dynamic random-access memory based on a metal-oxide-semiconductor field-effect transistor with a double-polysilicon layer structure has been proposed and investigated using technology computer-aided design simulation. By using the grain boundary for hole storage, a higher sensing margin of 4.35 /μA//μm is achieved compared to that without using the grain boundary. Furthermore, the proposed device achieves a superior retention time of 555.77 /μs, which is reasonable from the viewpoint of its application in embedded systems (>100 /μs), even at a high temperature of 358 K. For higher device reliability, the effect of the grain boundary on the capacitorless one-transistor embedded dynamic random-access memory is analyzed with different trap distributions. The proposed capacitorless one-transistor embedded dynamic random-access memory cell exhibited superior reliability in terms of retention time (>100 /μs).

scholarly journals One-Transistor Dynamic Random-Access Memory Based on Gate-All-Around Junction-Less Field-Effect Transistor with a Si/SiGe Heterostructure

Electronics ◽  
2020 ◽  
Vol 9 (12) ◽  
pp. 2134
Author(s):  
Young Jun Yoon ◽  
Jae Sang Lee ◽  
Dong-Seok Kim ◽  
Sang Ho Lee ◽  
In Man Kang
Keyword(s):  
Quantum Well ◽  
Retention Time ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Random Access ◽  
Random Access Memory ◽  
The Body ◽  
Access Memory ◽  
Effect Transistor ◽  
Memory Applications

This paper presents a one-transistor dynamic random-access memory (1T-DRAM) cell based on a gate-all-around junction-less field-effect transistor (GAA-JLFET) with a Si/SiGe heterostructure for high-density memory applications. The proposed 1T-DRAM achieves the sensing margin using the difference in hole density in the body region between ‘1’ and ‘0’ states. The Si/SiGe heterostructure forms a quantum well in the body and reduces the band-to-band tunneling (BTBT) barrier between the body and drain. Compared with the performances of the 1T-DRAM with Si homo-structure, the proposed 1T-DRAM improves the sensing margin and retention time because its storage ability is enhanced by the quantum well. In addition, the thin BTBT barrier reduced the bias condition for the program operation. The proposed 1T-DRAM showed a high potential for memory applications by obtaining a high read current ratio at ‘1’ and ‘0’ states about 108 and a long retention time above 10 ms.

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