A Parallel Transmission Scheme Based on the Turbo Product Code for Through Silicon via Array in Three-Dimensional Integrated Circuits

2021 ◽  
Vol 16 (3) ◽  
pp. 494-500
Author(s):  
Zhen-Song Li ◽  
Bing-Jie Li ◽  
Min Miao
Keyword(s):  
Integrated Circuits ◽  
Three Dimensional ◽  
Structural Defects ◽  
Transmission Performance ◽  
Crosstalk Noise ◽  
Transmission Scheme ◽  
Parallel Transmission ◽  
Through Silicon Via ◽  
Product Code ◽  
Turbo Product Code

Through silicon via (TSV) is the key technology for the vertical interconnect in three-dimensional integrated circuits (3-D ICs). With the help of TSVs, higher throughput in signal transmission can be attained. However, the tightly clustered TSVs in the TSV array suffer from crosstalk noise, a situation which results in transmission errors. This study investigates, the channel model of the TSV array, involving main factors affecting transmission performance, such as transmission loss, inter-channel interference, and crosstalk noise with different digital patterns. A parallel transmission scheme based on a turbo product code (TPC) parallel coding is proposed. In this scheme, the binary bits of information are reshaped into two dimensional blocks. Each block is parallel encoded using a TPC into a codeword block for parallel transmission through the TSV array channel. At the receiver, the sending information is reformed by a concurrent hard decision decoding algorithm of a TPC. This parallel transmission scheme achieves low bit-error-rate, high throughput, and a lower system overhead relative to that of its ground TSV shielded counterpart if the type of TPC is carefully selected. The simulation results confirm that this scheme reduces inter-symbol interference, minimizes structural defects in the TSV array, and improves transmission performance in 3-D ICs.

Through-silicon-via crosstalk model and optimization design for three-dimensional integrated circuits

2014 ◽  
Vol 23 (3) ◽  
pp. 038402
Author(s):  
Li-Bo Qian ◽  
Zhang-Ming Zhu ◽  
Yin-Shui Xia ◽  
Rui-Xue Ding ◽  
Yin-Tang Yang
Keyword(s):  
Integrated Circuits ◽  
Optimization Design ◽  
Three Dimensional ◽  
Through Silicon Via

The effective control of Cu through-silicon via extrusion for three-dimensional integrated circuits by a metallic cap layer

2019 ◽  
Vol 164 ◽  
pp. 101-104 ◽  
Author(s):  
Golareh Jalilvand ◽  
Omar Ahmed ◽  
Laura Spinella ◽  
Le Zhou ◽  
Tengfei Jiang
Keyword(s):  
Integrated Circuits ◽  
Three Dimensional ◽  
Effective Control ◽  
Through Silicon Via ◽  
Cap Layer

scholarly journals New coaxial through silicon via (TSV) applied for three dimensional integrated circuits (3D ICs)

2016 ◽  
Vol 13 (8) ◽  
pp. 20160192-20160192 ◽  
Author(s):  
Yintang Yang ◽  
Junping Zheng ◽  
Gang Dong ◽  
Yingbo Zhao ◽  
Zheng Mei ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Three Dimensional ◽  
Through Silicon Via ◽  
3D Ics

Scanning Electron Microscopy in Hybrid Microelectronics

1976 ◽  
Vol 34 ◽  
pp. 456-457
Author(s):  
S. Khadpe ◽  
R. Faryniak
Keyword(s):  
Integrated Circuits ◽  
Thick Film ◽  
Integrated Circuit ◽  
Failure Modes ◽  
Three Dimensional ◽  
Circuit Components ◽  
Hybrid Microcircuit ◽  
Electrical Connections ◽  
Scanning Electron

The Scanning Electron Microscope (SEM) is an important tool in Thick Film Hybrid Microcircuits Manufacturing because of its large depth of focus and three dimensional capability. This paper discusses some of the important areas in which the SEM is used to monitor process control and component failure modes during the various stages of manufacture of a typical hybrid microcircuit.Figure 1 shows a thick film hybrid microcircuit used in a Motorola Paging Receiver. The circuit consists of thick film resistors and conductors screened and fired on a ceramic (aluminum oxide) substrate. Two integrated circuit dice are bonded to the conductors by means of conductive epoxy and electrical connections from each integrated circuit to the substrate are made by ultrasonically bonding 1 mil aluminum wires from the die pads to appropriate conductor pads on the substrate. In addition to the integrated circuits and the resistors, the circuit includes seven chip capacitors soldered onto the substrate. Some of the important considerations involved in the selection and reliability aspects of the hybrid circuit components are: (a) the quality of the substrate; (b) the surface structure of the thick film conductors; (c) the metallization characteristics of the integrated circuit; and (d) the quality of the wire bond interconnections.

Silicon layers grown over SiO2 by liquid phase epitaxy: Electron Microscopical study

1990 ◽  
Vol 48 (4) ◽  
pp. 566-567
Author(s):  
F. Banhart ◽  
F.O. Phillipp ◽  
R. Bergmann ◽  
E. Czech ◽  
M. Konuma ◽  
...  
Keyword(s):  
Electron Microscopy ◽  
Liquid Phase ◽  
Plasma Etching ◽  
Liquid Phase Epitaxy ◽  
Three Dimensional ◽  
Microscopical Study ◽  
Sample Temperature ◽  
Structural Defects ◽  
Si Substrates ◽  
Etched Surface

Defect-free silicon layers grown on insulators (SOI) are an essential component for future three-dimensional integration of semiconductor devices. Liquid phase epitaxy (LPE) has proved to be a powerful technique to grow high quality SOI structures for devices and for basic physical research. Electron microscopy is indispensable for the development of the growth technique and reveals many interesting structural properties of these materials. Transmission and scanning electron microscopy can be applied to study growth mechanisms, structural defects, and the morphology of Si and SOI layers grown from metallic solutions of various compositions.The treatment of the Si substrates prior to the epitaxial growth described here is wet chemical etching and plasma etching with NF3 ions. At a sample temperature of 20°C the ion etched surface appeared rough (Fig. 1). Plasma etching at a sample temperature of −125°C, however, yields smooth and clean Si surfaces, and, in addition, high anisotropy (small side etching) and selectivity (low etch rate of SiO2) as shown in Fig. 2.

Analyzing the Impact of X-Ray Tomography on the Reliability of Integrated Circuits

2015 ◽  
Author(s):  
Halit Dogan ◽  
Md Mahbub Alam ◽  
Navid Asadizanjani ◽  
Sina Shahbazmohamadi ◽  
Domenic Forte ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
3D Imaging ◽  
Three Dimensional ◽  
Serial Sectioning ◽  
Promising Technique ◽  
Flash Memories ◽  
X Ray ◽  
3D Information ◽  
The Impact

Abstract X-ray tomography is a promising technique that can provide micron level, internal structure, and three dimensional (3D) information of an integrated circuit (IC) component without the need for serial sectioning or decapsulation. This is especially useful for counterfeit IC detection as demonstrated by recent work. Although the components remain physically intact during tomography, the effect of radiation on the electrical functionality is not yet fully investigated. In this paper we analyze the impact of X-ray tomography on the reliability of ICs with different fabrication technologies. We perform a 3D imaging using an advanced X-ray machine on Intel flash memories, Macronix flash memories, Xilinx Spartan 3 and Spartan 6 FPGAs. Electrical functionalities are then tested in a systematic procedure after each round of tomography to estimate the impact of X-ray on Flash erase time, read margin, and program operation, and the frequencies of ring oscillators in the FPGAs. A major finding is that erase times for flash memories of older technology are significantly degraded when exposed to tomography, eventually resulting in failure. However, the flash and Xilinx FPGAs of newer technologies seem less sensitive to tomography, as only minor degradations are observed. Further, we did not identify permanent failures for any chips in the time needed to perform tomography for counterfeit detection (approximately 2 hours).

Sign in / Sign up

Export Citation Format

Share Document