Dynamic Fault Tree (DFT) has drawn attention from comprehensive industrial systems in recent years. Many analytical approaches are developed to analyze DFT, such as Markov Chain based method, Inclusion-Exclusion Rule based method, and Sum-of-Disjoint-Product theory based method. Novel methods such as Bayesian Network and Petri Net are also used to solve DFT. However, Basic events are usually assumed unrepairable and are restricted to specific probabilistic distributions. And some methods may suffer from combination explosion. This paper applies Dynamic Uncertain Causality Graph (DUCG) to analyze DFT to overcome the aforementioned issues. DUCG is a newly proposed Probabilistic Graphic Model for large complex industrial systems which allows for dynamics, uncertainties and logic cycles. The DUCG based methodology can be summarized as event mapping, logical mapping, and numerical mapping. This paper studies how to map the PAND, FDEP, SEQ AND SPARE sequential logic gates into equivalent representations in DUCG. With the DUCG representation mode, one can analyze DFT with algorithms in DUCG. Future work will be done on benchmark tests and on software development.
Sequential Logic Circuits Using Spatial Wavefunction Switched (SWS) FETs
