scholarly journals Low-Area and Low-Power Circuit Implementation of Color Space Conversion between RGB and YCbCr

2016 ◽  
Vol 05 (04) ◽  
pp. 51-59
Author(s):  
斐 陆
2013 ◽  
Vol 37 (3) ◽  
pp. 959-970
Author(s):  
Ching-Yi Chen ◽  
Ching-Han Chen ◽  
Chih-Hao Ma ◽  
Po-Yi Wu

The main purpose of this paper is to investigate a novel design method using a genetic algorithm (GA) to automatically evolve the multiplierless CSC circuit architecture. In order to demonstrate the effectiveness of the described design method, several test images are adopted respectively to perform RGB to YCbCr color conversion experiment. The experimental results represent that the performance of the implemented hardware architecture is good when carrying out color space conversion from RGB to YCbCr. It also has the advantage of being high-speed, low-complexity, and low-area.


Processes ◽  
2021 ◽  
Vol 9 (7) ◽  
pp. 1128
Author(s):  
Chern-Sheng Lin ◽  
Yu-Ching Pan ◽  
Yu-Xin Kuo ◽  
Ching-Kun Chen ◽  
Chuen-Lin Tien

In this study, the machine vision and artificial intelligence algorithms were used to rapidly check the degree of cooking of foods and avoid the over-cooking of foods. Using a smart induction cooker for heating, the image processing program automatically recognizes the color of the food before and after cooking. The new cooking parameters were used to identify the cooking conditions of the food when it is undercooked, cooked, and overcooked. In the research, the camera was used in combination with the software for development, and the real-time image processing technology was used to obtain the information of the color of the food, and through calculation parameters, the cooking status of the food was monitored. In the second year, using the color space conversion, a novel algorithm, and artificial intelligence, the foreground segmentation was used to separate the vegetables from the background, and the cooking ripeness, cooking unevenness, oil glossiness, and sauce absorption were calculated. The image color difference and the distribution were used to judge the cooking conditions of the food, so that the cooking system can identify whether or not to adopt partial tumbling, or to end a cooking operation. A novel artificial intelligence algorithm is used in the relative field, and the error rate can be reduced to 3%. This work will significantly help researchers working in the advanced cooking devices.


Author(s):  
Peng Yin ◽  
Zhou Shu ◽  
Yingjun Xia ◽  
Tianmei Shen ◽  
Xiao Guan ◽  
...  
Keyword(s):  

2005 ◽  
Vol 15 (02) ◽  
pp. 459-476
Author(s):  
C. PATRICK YUE ◽  
JAEJIN PARK ◽  
RUIFENG SUN ◽  
L. RICK CARLEY ◽  
FRANK O'MAHONY

This paper presents the low-power circuit techniques suitable for high-speed digital parallel interfaces each operating at over 10 Gbps. One potential application for such high-performance I/Os is the interface between the channel IC and the magnetic read head in future compact hard disk systems. First, a crosstalk cancellation technique using a novel data encoding scheme is introduced to suppress electromagnetic interference (EMI) generated by the adjacent parallel I/Os . This technique is implemented utilizing a novel 8-4-PAM signaling with a data look-ahead algorithm. The key circuit components in the high-speed interface transceiver including the receive sampler, the phase interpolator, and the transmitter output driver are described in detail. Designed in a 0.13-μm digital CMOS process, the transceiver consumes 310 mW per 10-Gps channel from a I-V supply based on simulation results. Next, a 20-Gbps continuous-time adaptive passive equalizer utilizing on-chip lumped RLC components is described. Passive equalizers offer the advantages of higher bandwidth and lower power consumption compared with conventional designs using active filter. A low-power, continuous-time servo loop is designed to automatically adjust the equalizer frequency response for the optimal gain compensation. The equalizer not only adapts to different channel characteristics, but also accommodates temperature and process variations. Implemented in a 0.25-μm, 1P6M BiCMOS process, the equalizer can compensate up to 20 dB of loss at 10 GHz while only consumes 32 mW from a 2.5-V supply.


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