Design of Squarer Circuit in Sub-threshold Mode

Historically, analog designs have been assumed as a voltage mode based signal processing. However, the necessity of high speed circuits operating at reduced supply voltage has lead to a development of new circuit topology referred as current-mode designs. For low power low voltage designs the applications using translinear principle based circuits has become an area of research and interest. It has wide application in nonlinear signal processing and to build basic active elements. Mode of MOS transistor used in analog circuit realization of is important parameter deciding the performance of the circuit. In this paper, a squarer circuit is proposed based on sub threshold-mode MOS transistors exhibiting the exponential current-voltage characteristic. The simulations have been performed on model files of TSMC 0.18 micrometer technology with the help of ELDO Simulator.

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Investigation of PVT-Aware STT-MRAM Sensing Circuits for Low-VDD Scenario

Micromachines ◽

10.3390/mi12050551 ◽

2021 ◽

Vol 12 (5) ◽

pp. 551

Author(s):

Zhongjian Bian ◽

Xiaofeng Hong ◽

Yanan Guo ◽

Lirida Naviner ◽

Wei Ge ◽

...

Keyword(s):

Nonvolatile Memory ◽

High Speed ◽

Low Voltage ◽

Supply Voltage ◽

Random Access ◽

Magnetic Tunnel Junction ◽

Complementary Metal Oxide Semiconductor ◽

Current Mode ◽

Cmos Technology ◽

Oxide Semiconductor

Spintronic based embedded magnetic random access memory (eMRAM) is becoming a foundry validated solution for the next-generation nonvolatile memory applications. The hybrid complementary metal-oxide-semiconductor (CMOS)/magnetic tunnel junction (MTJ) integration has been selected as a proper candidate for energy harvesting, area-constraint and energy-efficiency Internet of Things (IoT) systems-on-chips. Multi-VDD (low supply voltage) techniques were adopted to minimize energy dissipation in MRAM, at the cost of reduced writing/sensing speed and margin. Meanwhile, yield can be severely affected due to variations in process parameters. In this work, we conduct a thorough analysis of MRAM sensing margin and yield. We propose a current-mode sensing amplifier (CSA) named 1D high-sensing 1D margin, high 1D speed and 1D stability (HMSS-SA) with reconfigured reference path and pre-charge transistor. Process-voltage-temperature (PVT) aware analysis is performed based on an MTJ compact model and an industrial 28 nm CMOS technology, explicitly considering low-voltage (0.7 V), low tunneling magnetoresistance (TMR) (50%) and high temperature (85 °C) scenario as the worst sensing case. A case study takes a brief look at sensing circuits, which is applied to in-memory bit-wise computing. Simulation results indicate that the proposed high-sensing margin, high speed and stability sensing-sensing amplifier (HMSS-SA) achieves remarkable performance up to 2.5 GHz sensing frequency. At 0.65 V supply voltage, it can achieve 1 GHz operation frequency with only 0.3% failure rate.

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MCML D-Latch Using Triple-Tail Cells: Analysis and Design

Active and Passive Electronic Components ◽

10.1155/2013/217674 ◽

2013 ◽

Vol 2013 ◽

pp. 1-9 ◽

Cited By ~ 17

Author(s):

Kirti Gupta ◽

Neeta Pandey ◽

Maneesha Gupta

Keyword(s):

High Speed ◽

Analytical Modeling ◽

Low Voltage ◽

Supply Voltage ◽

Current Mode ◽

Cmos Technology ◽

Power Efficient ◽

Analysis And Design ◽

Current Mode Logic ◽

Voltage Swing

A new low-voltage MOS current mode logic (MCML) topology for D-latch is proposed. The new topology employs a triple-tail cell to lower the supply voltage requirement in comparison to traditional MCML D-latch. The design of the proposed MCML D-latch is carried out through analytical modeling of its static parameters. The delay is expressed in terms of the bias current and the voltage swing so that it can be traded off with the power consumption. The proposed low-voltage MCML D-latch is analyzed for the two design cases, namely, high-speed and power-efficient, and the performance is compared with the traditional MCML D-latch for each design case. The theoretical propositions are validated through extensive SPICE simulations using TSMC 0.18 µm CMOS technology parameters.

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Advanced Low Power High Speed Nonlinear Signal Processing: An Analog VLSI Example.

Journal of Signal Processing Systems ◽

10.1007/s11265-016-1171-0 ◽

2016 ◽

Vol 89 (1) ◽

pp. 163-180 ◽

Cited By ~ 1

Author(s):

Giuseppe Oliveri ◽

Mohamad Mostafa ◽

Werner G. Teich ◽

Jürgen Lindner ◽

Hermann Schumacher

Keyword(s):

Signal Processing ◽

Low Power ◽

High Speed ◽

Analog Vlsi ◽

Nonlinear Signal Processing ◽

Nonlinear Signal

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A low-noise current preamplifier in 120 nm CMOS technology

Advances in Radio Science ◽

10.5194/ars-6-213-2008 ◽

2008 ◽

Vol 6 ◽

pp. 213-217 ◽

Cited By ~ 1

Author(s):

H. Uhrmann ◽

W. Gaberl ◽

H. Zimmermann

Keyword(s):

High Speed ◽

Analog Circuit ◽

Low Voltage ◽

Supply Voltage ◽

Cmos Technology ◽

Low Noise ◽

Special Focus ◽

Current Mirror ◽

Chip Area ◽

The Impact

Abstract. In this paper we examine the impact of deep sub-micron CMOS technology on analog circuit design with a special focus on the noise performance and the ability to design low-noise preamplifiers. To point out, why CMOS technology can grow to a key technology in low-noise and high-speed applications, various amplifier stages, applied in literature, are compared. One, that fits as a current preamplifier for low-noise applications, is the current mirror. Starting from the basic current mirror, an enhanced current preamplifier is developed, that offers low-noise and high-speed operation. The suggested chip is realized in 0.12 μm CMOS technology and needs a chip area of 100 μm×280 μm. It consumes about 15 mW at a supply voltage of 1.5 V. The presented current preamplifier has a bandwidth of 750 MHz and a gain of 36 dB. The fields of application for current preamplifiers are, for instance, charge amplifiers, amplifiers for low-voltage differential signaling (LVDS) based point-to-point data links or preamplifiers for photodetectors.

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