scholarly journals A low-noise current preamplifier in 120 nm CMOS technology

2008 ◽  
Vol 6 ◽  
pp. 213-217 ◽  
Author(s):  
H. Uhrmann ◽  
W. Gaberl ◽  
H. Zimmermann
Keyword(s):  
High Speed ◽  
Analog Circuit ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Low Noise ◽  
Special Focus ◽  
Current Mirror ◽  
Chip Area ◽  
The Impact

Abstract. In this paper we examine the impact of deep sub-micron CMOS technology on analog circuit design with a special focus on the noise performance and the ability to design low-noise preamplifiers. To point out, why CMOS technology can grow to a key technology in low-noise and high-speed applications, various amplifier stages, applied in literature, are compared. One, that fits as a current preamplifier for low-noise applications, is the current mirror. Starting from the basic current mirror, an enhanced current preamplifier is developed, that offers low-noise and high-speed operation. The suggested chip is realized in 0.12 μm CMOS technology and needs a chip area of 100 μm×280 μm. It consumes about 15 mW at a supply voltage of 1.5 V. The presented current preamplifier has a bandwidth of 750 MHz and a gain of 36 dB. The fields of application for current preamplifiers are, for instance, charge amplifiers, amplifiers for low-voltage differential signaling (LVDS) based point-to-point data links or preamplifiers for photodetectors.

scholarly journals Investigation of PVT-Aware STT-MRAM Sensing Circuits for Low-VDD Scenario

Micromachines ◽  
2021 ◽  
Vol 12 (5) ◽  
pp. 551
Author(s):  
Zhongjian Bian ◽  
Xiaofeng Hong ◽  
Yanan Guo ◽  
Lirida Naviner ◽  
Wei Ge ◽  
...  
Keyword(s):  
Nonvolatile Memory ◽  
High Speed ◽  
Low Voltage ◽  
Supply Voltage ◽  
Random Access ◽  
Magnetic Tunnel Junction ◽  
Complementary Metal Oxide Semiconductor ◽  
Current Mode ◽  
Cmos Technology ◽  
Oxide Semiconductor

Spintronic based embedded magnetic random access memory (eMRAM) is becoming a foundry validated solution for the next-generation nonvolatile memory applications. The hybrid complementary metal-oxide-semiconductor (CMOS)/magnetic tunnel junction (MTJ) integration has been selected as a proper candidate for energy harvesting, area-constraint and energy-efficiency Internet of Things (IoT) systems-on-chips. Multi-VDD (low supply voltage) techniques were adopted to minimize energy dissipation in MRAM, at the cost of reduced writing/sensing speed and margin. Meanwhile, yield can be severely affected due to variations in process parameters. In this work, we conduct a thorough analysis of MRAM sensing margin and yield. We propose a current-mode sensing amplifier (CSA) named 1D high-sensing 1D margin, high 1D speed and 1D stability (HMSS-SA) with reconfigured reference path and pre-charge transistor. Process-voltage-temperature (PVT) aware analysis is performed based on an MTJ compact model and an industrial 28 nm CMOS technology, explicitly considering low-voltage (0.7 V), low tunneling magnetoresistance (TMR) (50%) and high temperature (85 °C) scenario as the worst sensing case. A case study takes a brief look at sensing circuits, which is applied to in-memory bit-wise computing. Simulation results indicate that the proposed high-sensing margin, high speed and stability sensing-sensing amplifier (HMSS-SA) achieves remarkable performance up to 2.5 GHz sensing frequency. At 0.65 V supply voltage, it can achieve 1 GHz operation frequency with only 0.3% failure rate.

A CMOS Automatic Gain Control Circuit for Biomedical Applications

2015 ◽  
Vol 645-646 ◽  
pp. 1308-1313
Author(s):  
Zhi Qiang Gao ◽  
Fu Xiang Huang ◽  
Jing Li ◽  
Liang Yin ◽  
Xiao Wei Liu
Keyword(s):  
Exponential Function ◽  
Biomedical Applications ◽  
Low Voltage ◽  
Supply Voltage ◽  
Automatic Gain Control ◽  
Gain Control ◽  
Cmos Technology ◽  
Chip Area ◽  
Gain Variation ◽  
Linearity Error

In this paper, a low-voltage automatic gain control (AGC) circuits is presented. The proposed circuit uses a novel approximated exponential function to increase the dB-linear output range. The three-stage AGC is fabricated in 0.18μm CMOS technology and shows the maximum gain variation of more than 100dB and a 67dB linear range with linearity error of less than ±1dB. The range of gain variation can be controlled from 34 to 101dB. The AGC dissipates less than 2.3mA under 1.8V supply voltage while occupying 0.4mm2 of chip area.

scholarly journals Low-Power High-Speed Double Gate 1-bit Full Adder Cell

2016 ◽  
Vol 62 (4) ◽  
pp. 329-334 ◽  
Author(s):  
Raushan Kumar ◽  
Sahadev Roy ◽  
C.T. Bhunia
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Low Voltage ◽  
Supply Voltage ◽  
Average Power ◽  
Full Adder ◽  
Cmos Technology ◽  
Spice Simulation ◽  
Pass Transistor ◽  
Voltage Swing

Abstract In this paper, we proposed an efficient full adder circuit using 16 transistors. The proposed high-speed adder circuit is able to operate at very low voltage and maintain the proper output voltage swing and also balance the power consumption and speed. Proposed design is based on CMOS mixed threshold voltage logic (MTVL) and implemented in 180nm CMOS technology. In the proposed technique the most time-consuming and power consuming XOR gates and multiplexer are designed using MTVL scheme. The maximum average power consumed by the proposed circuit is 6.94μW at 1.8V supply voltage and frequency of 500 MHz, which is less than other conventional methods. Power, delay, and area are optimized by using pass transistor logic and verified using the SPICE simulation tool at desired broad frequency range. It is also observed that the proposed design may be successfully utilized in many cases, especially whenever the lowest power consumption and delay are aimed.

A Novel CNFET Technology Based 3 Bit Flash ADC for Low-Voltage High Speed SoC Application

2015 ◽  
Vol 19 ◽  
pp. 19-36 ◽  
Author(s):  
P.A. Gowri Sankar ◽  
G. Sathiyabama
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Circuit Design ◽  
Field Effect ◽  
High Speed ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Flash Adc ◽  
Simulation Results

The continuous scaling down of metal-oxide-semiconductor field effect transistors (MOSFETs) led to the considerable impact in the analog-digital mixed signal integrated circuit design for system-on-chips (SoCs) application. SoCs trends force ADCs to be integrated on the chip with other digital circuits. These trends present new challenges in ADC circuit design based on existing CMOS technology. In this paper, we have designed and analyzed a 3-bit high speed, low-voltage and low-power flash ADC at 32nm CNFET technology for SoC applications. The proposed ADC utilizes the Threshold Inverter Quantization (TIQ) technique that uses two cascaded carbon nanotube field effect transistor (CNFET) inverters as a comparator. The TIQ technique proposed has been developed for better implementation in SoC applications. The performance of the proposed ADC is studied using two different types of encoders such as ROM and Fat tree encoders. The proposed ADCs circuits are simulated using Synopsys HSPICE with standard 32nm CNFET model at 0.9 input supply voltage. The simulation results show that the proposed 3 bit TIQ technique based flash ADC with fat tree encoder operates up to 8 giga samples per second (GSPS) with 35.88µW power consumption. From the simulation results, we observed that the proposed TIQ flash ADC achieves high speed, small size, low power consumption, and low voltage operation compared to other low power CMOS technology based flash ADCs. The proposed method is sensitive to process, temperature and power supply voltage variations and their impact on the ADC performance is also investigated.

COMPLEMENTARY AND DOUBLE-EDGE BASED: A 5-BIT CMOS DIGITAL PULSE-WIDTH MODULATION (PWM) DESIGN WITH MULTIPLE OUTPUTS FOR LED DIMMING APPLICATION

2014 ◽  
Vol 23 (02) ◽  
pp. 1450030 ◽  
Author(s):  
YU-CHERNG HUNG
Keyword(s):  
Pulse Width ◽  
High Speed ◽  
Pulse Width Modulation ◽  
Supply Voltage ◽  
Light Emitting Diode ◽  
Cmos Technology ◽  
Chip Area ◽  
Double Edge ◽  
Digital Pulse ◽  
Dimming Control

In this paper, a compact high-precision digital pulse-width modulation (DPWM) CMOS circuit is proposed. The circuit, with multiple output capability, allows brightness control of red, green, and blue (RGB) light emitting diode (LED) lighting. The PWM technique is used for LED dimming control to avoid the problem of color shifting. In this design, complementary concepts and hardware sharing are utilized to achieve a compact architecture and small chip area. A double-edge triggered technique is adopted to enhance the capability of high-speed operation. An experimental chip has been realized by using TSMC 0.18-μm CMOS technology. Simulation results show that the proposed 5-bit PWM circuit can operate at 200 MHz, 32 duty cycles adjustable, and within only 1-ns time error. The chip's measured results show that the new PWM circuit with three output channels works successfully at a supply voltage of 1.8-V, clock of 50-MHz, and resolution of 32 adjustable per channel. The core area of the chip is only 280 × 52.5 μm2.

A Low-Voltage Low-Power Resistor-Based Current Mirror and Its Applications

2017 ◽  
Vol 26 (11) ◽  
pp. 1750180 ◽  
Author(s):  
Leila Safari ◽  
Shahram Minaei
Keyword(s):  
Output Voltage ◽  
High Performance ◽  
Low Voltage ◽  
Supply Voltage ◽  
Input Voltage ◽  
Cmos Technology ◽  
Current Mirror ◽  
Output Impedance ◽  
High Cmrr ◽  
High Output Impedance

In this paper, a CMOS resistor-based current mirror (RBCM) aimed to be used in low-voltage applications is presented. The main features of the proposed current mirror are very low input voltage requirement (a few mV), low output voltage requirement, high output impedance and simple circuitry. The core structure of the proposed RBCM consists of three transistors (excluding bias circuitry) and two low value grounded resistors. The proposed circuit alleviates the need for cascode structures which are conventionally used to boost the output impedance and linearity. SPICE simulations using 0.18[Formula: see text][Formula: see text]m CMOS technology parameters under supply voltage of 0.9[Formula: see text]V are reported which show input and output voltage requirements of 40[Formula: see text]mV and 0.1[Formula: see text]V respectively, low THD of 1.2%, [Formula: see text] of 496[Formula: see text][Formula: see text], [Formula: see text] of 1[Formula: see text]M[Formula: see text], [Formula: see text]3[Formula: see text]dB bandwidth of 181[Formula: see text]MHz and power dissipation of 154[Formula: see text][Formula: see text]W. A high CMRR differential amplifier and a high performance current difference circuit as applications of the proposed RBCM are given. The proposed RBCM is very useful in tackling restrictions of modern technologies such as reduced supply voltage and transistors low intrinsic output impedance.

scholarly journals Ultra-Low-Voltage CMOS-Based Current Bleeding Mixer with High LO-RF Isolation

2014 ◽  
Vol 2014 ◽  
pp. 1-5 ◽  
Author(s):  
Gim Heng Tan ◽  
Roslina Mohd Sidek ◽  
Harikrishnan Ramiah ◽  
Wei Keat Chong ◽  
De Xing Lioe
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Third Order ◽  
Chip Area ◽  
Integrated Inductors ◽  
Low Voltage Operation ◽  
Dc Power ◽  
Current Bleeding ◽  
Intercept Point

This journal presents an ultra-low-voltage current bleeding mixer with high LO-RF port-to-port isolation, implemented on 0.13 μm standard CMOS technology for ZigBee application. The architecture compliments a modified current bleeding topology, consisting of NMOS-based current bleeding transistor, PMOS-based switching stage, and integrated inductors achieving low-voltage operation and high LO-RF isolation. The mixer exhibits a conversion gain of 7.5 dB at the radio frequency (RF) of 2.4 GHz, an input third-order intercept point (IIP3) of 1 dBm, and a LO-RF isolation measured to 60 dB. The DC power consumption is 572 µW at supply voltage of 0.45 V, while consuming a chip area of 0.97 × 0.88 mm2.

scholarly journals A Low-Voltage, Low-Power Reconfigurable Current-Mode Softmax Circuit for Analog Neural Networks

Electronics ◽  
2021 ◽  
Vol 10 (9) ◽  
pp. 1004
Author(s):  
Massimo Vatalaro ◽  
Marco Lanuzza ◽  
Felice Crupi ◽  
Tatiana Moposita ◽  
Lionel Trojman ◽  
...  
Keyword(s):  
Low Power ◽  
Modular Design ◽  
Low Voltage ◽  
Supply Voltage ◽  
Current Mode ◽  
Cmos Technology ◽  
Chip Area ◽  
Analog Implementation ◽  
Efficient Option ◽  
P Type

This paper presents a novel low-power low-voltage analog implementation of the softmax function, with electrically adjustable amplitude and slope parameters. We propose a modular design, which can be scaled by the number of inputs (and of corresponding outputs). It is composed of input current–voltage linear converter stages (1st stages), MOSFETs operating in a subthreshold regime implementing the exponential functions (2nd stages), and analog divider stages (3rd stages). Each stage is only composed of p-type MOSFET transistors. Designed in a 0.18 µm CMOS technology (TSMC), the proposed softmax circuit can be operated at a supply voltage of 500 mV. A ten-input/ten-output realization occupies a chip area of 2570 µm2 and consumes only 3 µW of power, representing a very compact and energy-efficient option compared to the corresponding digital implementations.

scholarly journals Design of Squarer Circuit in Sub-threshold Mode

2018 ◽  
Vol 7 (2.11) ◽  
pp. 38
Author(s):  
Bindu Thakral ◽  
Arti Vaish ◽  
Rama Koteswara Rao Alla
Keyword(s):  
Signal Processing ◽  
High Speed ◽  
Analog Circuit ◽  
Low Voltage ◽  
Supply Voltage ◽  
Current Mode ◽  
Nonlinear Signal Processing ◽  
Circuit Realization ◽  
Mos Transistor ◽  
Nonlinear Signal

Historically, analog designs have been assumed as a voltage mode based signal processing. However, the necessity of high speed circuits operating at reduced supply voltage has lead to a development of new circuit topology referred as current-mode designs. For low power low voltage designs the applications using translinear principle based circuits has become an area of research and interest. It has wide application in nonlinear signal processing and to build basic active elements. Mode of MOS transistor used in analog circuit realization of is important parameter deciding the performance of the circuit. In this paper, a squarer circuit is proposed based on sub threshold-mode MOS transistors exhibiting the exponential current-voltage characteristic. The simulations have been performed on model files of TSMC 0.18 micrometer technology with the help of ELDO Simulator. 

scholarly journals Bandwidth Extension of High Compliance Current Mirror by Using Compensation Methods

2014 ◽  
Vol 2014 ◽  
pp. 1-8 ◽  
Author(s):  
Maneesha Gupta ◽  
Urvashi Singh ◽  
Richa Srivastava
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
Low Voltage ◽  
Cmos Technology ◽  
Current Mirror ◽  
Bandwidth Extension ◽  
High Compliance ◽  
Compensation Methods ◽  
Inductive Peaking ◽  
Cascode Current Mirror

Due to the huge demand of high-speed analog integrated circuits, it is essential to develop a wideband low input impedance current mirror that can be operated at low power supply. In this paper, a novel wideband low voltage high compliance current mirror using low voltage cascode current mirror (LVCCM) as a basic building block is proposed. The resistive compensation and inductive peaking methods have been used to extend the bandwidth of the conventional current mirror. By replacing conventional LVCCM in a high compliance current mirror with the compensated LVCCM, the bandwidth extension ratio of 3.4 has been achieved with no additional DC power dissipation and without affecting its other performances. The circuits are designed in TSMC 0.18 μm CMOS technology on Spectre simulator of Cadence.

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