scholarly journals Testing embedded systems using test cases generated through combinatorial techniques

2018 ◽  
Vol 7 (2.7) ◽  
pp. 146
Author(s):  
Lakshmi Prasad Mudarakola ◽  
J K.R. Sastry ◽  
V Chandra Prakash
Keyword(s):  
Embedded Systems ◽  
Embedded System ◽  
Traffic Control ◽  
Nuclear Reactor ◽  
Test Cases ◽  
Critical Systems ◽  
Daily Lives ◽  
Intelligent Devices ◽  
Wireless Infrastructure ◽  
Combinatorial Methods

Thorough testing of embedded systems is required especially when the systems are related to monitoring and controlling the mission critical and safety critical systems. The embedded systems must be tested comprehensively which include testing hardware, software and both together. Embedded systems are highly intelligent devices that are infiltrating our daily lives such as the mobile in your pocket, and wireless infrastructure behind it, routers, home theatre system, the air traffic control station etc. Software now makes up 90% of the value of these devices. In this paper, authors present different methods to test an embedded system using test cases generated through combinatorial techniques. The experimental results for testing a TMCNRS (Temperature Monitoring and Controlling Nuclear Reactor System) using test cases generated from combinatorial methods are also shown.

scholarly journals Networking Heterogeneous Microcontroller based Systems through Universal Serial Bus

2015 ◽  
Vol 5 (5) ◽  
pp. 992
Author(s):  
Sastry Kodanda Rama Jammalamadaka ◽  
Valluru Sai Kumar Reddy ◽  
Smt J Sasi Bhanu
Keyword(s):  
Embedded Systems ◽  
Embedded System ◽  
Error Detection ◽  
Nuclear Reactor ◽  
Universal Serial Bus ◽  
Distributed Embedded Systems ◽  
Communication Architecture ◽  
The Individual ◽  
And Control ◽  
Synchronisation Error

Networking heterogeneous embedded systems is a challenge. Every distributed embedded systems requires that the network is designed specifically considering the heterogeneity that exits among different Microcontroller based systems that are used in developing a distributed embedded system. Communication architecture, which considers the addressing of the individual systems, arbitration, synchronisation, error detection and control etc., needs to be designed considering a specific application. The issue of configuring the slaves has to be addressed. It is also important that the messages, flow of the messages across the individual ES systems must be designed. Every distributed embedded system is different and needs to be dealt with separately. This paper presents an approach that addresses various issues related to networking distributed embedded systems through use of universal serial bus communication protocol (USB). The approach has been applied to design a distributed embedded that monitors and controls temperatures within a Nuclear reactor system.

scholarly journals A Neural Network Based Strategy (NNBS) for Automated Construction of Test Cases for Testing an Embedded System using Combinatorial Techniques

2017 ◽  
Vol 7 (1.3) ◽  
pp. 74
Author(s):  
Lakshmi Prasad Mudarakola ◽  
J. K. R. Sastry
Keyword(s):  
Neural Network ◽  
Embedded Systems ◽  
Embedded System ◽  
Test Case ◽  
Test Cases ◽  
Paper Test ◽  
Testing Tools ◽  
System A ◽  
The Neural Network ◽  
Important Concern

Testing an embedded system is required to locate bugs in software, diminish risk, development, repairs costs and to improve performance for both users and the company. Embedded software testing tools are useful for catching defects during unit, integration and system testing.   Embedded systems in many cases must be optimized by engaging crucial areas of the embedded systems considering all factors of the input domain.  The most important concern is to build a place of test cases depend on design of the requirements that can recognize more number of faults at a least rate and point in time in the major sections of an embedded system. This paper proposes a Neural Network Based strategy (NNBS) to generate optimized test cases based on the considerations of the system. A tool called NNTCG (Neural Network Test Case Generator) has been build up based on the method proposed in this paper. Test cases are generated for testing an embedded system using NNTCG and the same are used to determine the expected output through the neural network and the output generated from the actual firmware. The faulty paths within the firmware are determined when the output generated by the neural network is not same as the output generated by the firmware.

scholarly journals Testing embedded system through optimal mining technique (OMT) based on multi-input domain

2019 ◽  
Vol 9 (3) ◽  
pp. 2141
Author(s):  
J. K. R. Sastry ◽  
M. Lakshmi Prasad
Keyword(s):  
Embedded Systems ◽  
Embedded System ◽  
Nuclear Reactors ◽  
The Other ◽  
Test Cases ◽  
Mining Technique ◽  
Other Hand ◽  
Input Domain

<p class="Abstract">Testing embedded systems must be done carefully particularly in the significant regions of the embedded systems. Inputs from an embedded system can happen in multiple order and many relationships can exist among the input sequences. Consideration of the sequences and the relationships among the sequences is one of the most important considerations that must be tested to find the expected behavior of the embedded systems. On the other hand combinatorial approaches help determining fewer test cases that are quite enough to test the embedded systems exhaustively. In this paper, an Optimal Mining Technique that considers multi-input domain which is based on built-in combinatorial approaches has been presented. The method exploits multi-input sequences and the relationships that exist among multi-input vectors. The technique has been used for testing an embedded system that monitors and controls the temperature within the Nuclear reactors.</p>

scholarly journals Implementing Syntax Evolution of Embedded Systems

2015 ◽  
Vol 5 (6) ◽  
pp. 1525
Author(s):  
Sasi Bhanu Jammalamadaka ◽  
Vinaya Babu A ◽  
Trimurthy P
Keyword(s):  
Embedded Systems ◽  
Embedded System ◽  
Critical Systems ◽  
Internet Communication ◽  
Critical System ◽  
Safety Critical ◽  
Safety Critical System ◽  
Remote Locations ◽  
Safety Critical Systems ◽  
The Embedded System

<p>Safety critical systems such as nuclear recator systems cannot be shutdown as restrating is a huge process and incurs heavy cost.  The embedded systems which are used for monitoring and controlling the safety critival systems cannot be shut down as well. ES systems which drives safety critical systems must be communicated from remote locations generally through a HOST connected on to Internet. Communication between the HOST and ES system is done using commnd lanaguage which has to be evolved from time to time.  The chnage to the commnd lanauage must be undertaken while the embedded system is up and running, the evolution thus must be dynamic. Many architetcuers have been propsoed in the lieteratuer for evolving  synatx of command lanaguage.The implemntaion of effcient architetcuer as such has not been found in the literatuer without which existing architetcuer as such has no menaing.</p><p>The paper presntes a set of methods using which the syntax evolution of embedded systems as such can be achived. The synatx evolution methods have been applied to a safety critical system that monitors and controls tempartuers within a Nuclear recator system.</p>

Analysis of Physicality Aspects in Physical User Interfaces of Embedded Systems

2013 ◽  
Vol 61 (1) ◽  
Author(s):  
Mahmood Ashraf ◽  
Masitah Ghazali
Keyword(s):  
Embedded Systems ◽  
Embedded System ◽  
User Interfaces ◽  
Natural Interaction ◽  
Daily Lives ◽  
Sound System ◽  
Evaluation Approach ◽  
Key Factor ◽  
The Embedded System ◽  
Result Analysis

Embedded systems are becoming more significant in our daily lives with the advent of ubiquitous computing. The increasing demands of multifarious functionalities and other factors lead to an increased focus of development on internal software issues. Negligence towards the interaction aspects of physical interface is resulting in the generation of interaction complexities for the user. This work evaluates, compares, and highlights the significance of physicality aspects of embedded system interfaces using five subjects including; washing machine; camera; oven; sound system; and MP3 player. The quantitative evaluation approach helps in a simple investigation by applying the numeric values for each aspect. The result analysis highlights the significance of exposed state, tangible transition, and inverse action over other physicality aspects. This study is especially valuable for the embedded system developers who may not have exposure or expertise to Human–Computer Interaction or its sub–field, Physicality. Managing and incorporating physicality aspects in embedded systems is a key factor for producing natural interaction products.

Compiler-Aided Run-Time Performance Speed-Up in Super-Scalar Processor

10.28945/3391 ◽  
2009 ◽  
Author(s):  
Moshe Pelleh
Keyword(s):  
Embedded Systems ◽  
Embedded System ◽  
General Purpose ◽  
Experimental Results ◽  
Medium Size ◽  
Organic System ◽  
Software Application ◽  
Organic Systems ◽  
Special Cases ◽  
Run Time

In our world, where most systems become embedded systems, the approach of designing embedded systems is still frequently similar to the approach of designing organic systems (or not embedded systems). An organic system, like a personal computer or a work station, must be able to run any task submitted to it at any time (with certain constrains depending on the machine). Consequently, it must have a sophisticated general purpose Operating System (OS) to schedule, dispatch, maintain and monitor the tasks and assist them in special cases (particularly communication and synchronization between them and with external devices). These OSs require an overhead on the memory, on the cache and on the run time. Moreover, generally they are task oriented rather than machine oriented; therefore the processor's throughput is penalized. On the other hand, an embedded system, like an Anti-lock Braking System (ABS), executes always the same software application. Frequently it is a small or medium size system, or made up of several such systems. Many small or medium size embedded systems, with limited number of tasks, can be scheduled by our proposed hardware architecture, based on the Motorola 500MHz MPC7410 processor, enhancing its throughput and avoiding the software OS overhead, complexity, maintenance and price. Encouraged by our experimental results, we shall develop a compiler to assist our method. In the meantime we will present here our proposal and the experimental results.

scholarly journals A Novel Rail-Network Hardware Simulator for Embedded System Programming

Electronics ◽  
2020 ◽  
Vol 10 (1) ◽  
pp. 13
Author(s):  
Balaji M ◽  
Chandrasekaran M ◽  
Vaithiyanathan Dhandapani
Keyword(s):  
Embedded Systems ◽  
Embedded System ◽  
Real Time ◽  
Learning Outcomes ◽  
Real World ◽  
Time Constraints ◽  
Network Simulator ◽  
Practical Applications ◽  
Rail Network ◽  
Knowledge Enhancement

A Novel Rail-Network Hardware with simulation facilities is presented in this paper. The hardware is designed to facilitate the learning of application-oriented, logical, real-time programming in an embedded system environment. The platform enables the creation of multiple unique programming scenarios with variability in complexity without any hardware changes. Prior experimental hardware comes with static programming facilities that focus the students’ learning on hardware features and programming basics, leaving them ill-equipped to take up practical applications with more real-time constraints. This hardware complements and completes their learning to help them program real-world embedded systems. The hardware uses LEDs to simulate the movement of trains in a network. The network has train stations, intersections and parking slots where the train movements can be controlled by using a 16-bit Renesas RL78/G13 microcontroller. Additionally, simulating facilities are provided to enable the students to navigate the trains by manual controls using switches and indicators. This helps them get an easy understanding of train navigation functions before taking up programming. The students start with simple tasks and gradually progress to more complicated ones with real-time constraints, on their own. During training, students’ learning outcomes are evaluated by obtaining their feedback and conducting a test at the end to measure their knowledge acquisition during the training. Students’ Knowledge Enhancement Index is originated to measure the knowledge acquired by the students. It is observed that 87% of students have successfully enhanced their knowledge undergoing training with this rail-network simulator.

scholarly journals A Generalization Performance Study Using Deep Learning Networks in Embedded Systems

Sensors ◽  
2021 ◽  
Vol 21 (4) ◽  
pp. 1031
Author(s):  
Joseba Gorospe ◽  
Rubén Mulero ◽  
Olatz Arbelaitz ◽  
Javier Muguerza ◽  
Miguel Ángel Antón
Keyword(s):  
Deep Learning ◽  
Embedded Systems ◽  
Embedded System ◽  
General Purpose ◽  
Learning Networks ◽  
Performance Study ◽  
Learning Techniques ◽  
Wide Range ◽  
Learning Architectures

Deep learning techniques are being increasingly used in the scientific community as a consequence of the high computational capacity of current systems and the increase in the amount of data available as a result of the digitalisation of society in general and the industrial world in particular. In addition, the immersion of the field of edge computing, which focuses on integrating artificial intelligence as close as possible to the client, makes it possible to implement systems that act in real time without the need to transfer all of the data to centralised servers. The combination of these two concepts can lead to systems with the capacity to make correct decisions and act based on them immediately and in situ. Despite this, the low capacity of embedded systems greatly hinders this integration, so the possibility of being able to integrate them into a wide range of micro-controllers can be a great advantage. This paper contributes with the generation of an environment based on Mbed OS and TensorFlow Lite to be embedded in any general purpose embedded system, allowing the introduction of deep learning architectures. The experiments herein prove that the proposed system is competitive if compared to other commercial systems.

scholarly journals Singular Value Decomposition in Embedded Systems Based on ARM Cortex-M Architecture

Electronics ◽  
2020 ◽  
Vol 10 (1) ◽  
pp. 34
Author(s):  
Michele Alessandrini ◽  
Giorgio Biagetti ◽  
Paolo Crippa ◽  
Laura Falaschetti ◽  
Lorenzo Manoni ◽  
...  
Keyword(s):  
Embedded Systems ◽  
Singular Value Decomposition ◽  
Embedded System ◽  
Mimo Systems ◽  
Singular Value ◽  
Measurement Unit ◽  
Comprehensive Treatment ◽  
Mathematical Tool ◽  
Value Decomposition ◽  
Speed Accuracy

Singular value decomposition (SVD) is a central mathematical tool for several emerging applications in embedded systems, such as multiple-input multiple-output (MIMO) systems, data analytics, sparse representation of signals. Since SVD algorithms reduce to solve an eigenvalue problem, that is computationally expensive, both specific hardware solutions and parallel implementations have been proposed to overcome this bottleneck. However, as those solutions require additional hardware resources that are not in general available in embedded systems, optimized algorithms are demanded in this context. The aim of this paper is to present an efficient implementation of the SVD algorithm on ARM Cortex-M. To this end, we proceed to (i) present a comprehensive treatment of the most common algorithms for SVD, providing a fairly complete and deep overview of these algorithms, with a common notation, (ii) implement them on an ARM Cortex-M4F microcontroller, in order to develop a library suitable for embedded systems without an operating system, (iii) find, through a comparative study of the proposed SVD algorithms, the best implementation suitable for a low-resource bare-metal embedded system, (iv) show a practical application to Kalman filtering of an inertial measurement unit (IMU), as an example of how SVD can improve the accuracy of existing algorithms and of its usefulness on a such low-resources system. All these contributions can be used as guidelines for embedded system designers. Regarding the second point, the chosen algorithms have been implemented on ARM Cortex-M4F microcontrollers with very limited hardware resources with respect to more advanced CPUs. Several experiments have been conducted to select which algorithms guarantee the best performance in terms of speed, accuracy and energy consumption.

scholarly journals The Design of a 2D Graphics Accelerator for Embedded Systems

Electronics ◽  
2021 ◽  
Vol 10 (4) ◽  
pp. 469
Author(s):  
Hyun Woo Oh ◽  
Ji Kwang Kim ◽  
Gwan Beom Hwang ◽  
Seung Eun Lee
Keyword(s):  
Embedded Systems ◽  
Embedded System ◽  
Real Time ◽  
Line Drawing ◽  
Cmos Process ◽  
Embedded Processor ◽  
Processor Core ◽  
Field Programmable ◽  
The Embedded System ◽  
Graphics Processing

Recently, advances in technology have enabled embedded systems to be adopted for a variety of applications. Some of these applications require real-time 2D graphics processing running on limited design specifications such as low power consumption and a small area. In order to satisfy such conditions, including a specific 2D graphics accelerator in the embedded system is an effective method. This method reduces the workload of the processor in the embedded system by exploiting the accelerator. The accelerator assists the system to perform 2D graphics processing in real-time. Therefore, a variety of applications that require 2D graphics processing can be implemented with an embedded processor. In this paper, we present a 2D graphics accelerator for tiny embedded systems. The accelerator includes an optimized line-drawing operation based on Bresenham’s algorithm. The optimized operation enables the accelerator to deal with various kinds of 2D graphics processing and to perform the line-drawing instead of the system processor. Moreover, the accelerator also distributes the workload of the processor core by removing the need for the core to access the frame buffer memory. We measure the performance of the accelerator by implementing the processor, including the accelerator, on a field-programmable gate array (FPGA), and ascertaining the possibility of realization by synthesizing using the 180 nm CMOS process.

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