Design of a Miniaturized Class F Power Amplifier Using Capacitor Loaded Transmission Lines

Frequenz ◽  
2020 ◽  
Vol 74 (3-4) ◽  
pp. 145-152
Author(s):  
Ali Pirasteh ◽  
Saeed Roshani ◽  
Sobhan Roshani
Keyword(s):  
Power Amplifier ◽  
Mobile Communications ◽  
Transmission Lines ◽  
Low Voltage ◽  
Good Choice ◽  
Band Frequency ◽  
Power Added Efficiency ◽  
Harmonic Control ◽  
Measurement Results ◽  
Class F

AbstractIn this paper, a new method to decrease the dimensions of the microstrip structures and reducing the overall size of the class F amplifiers is presented. First, by using the PHEMT transistor with a conventional harmonic control circuit (HCC), a low-voltage class F amplifier in the L band frequency at the operating frequency of 1.75 GHz is introduced, which named primitive class F power amplifier. Then, this amplifier is optimized by using capacitor loaded transmission lines (CLTLs). The measurement results of the amplifier show that by using the CLTL structure, the overall size has been reduced 85% (0.23 λg × 0.17 λg). The maximum power-added efficiency (PAE) of the power amplifier is about 77.5 % and the power gain which has been reached to 18.33 dB. The desirable features of this power amplifier, along with its very small size, make this power amplifier a good choice to use for the global system for mobile communications.

High-efficiency inverse class-F power amplifier using 3/4 spiral symmetric defected ground structure

2011 ◽  
Vol 3 (6) ◽  
pp. 621-625
Author(s):  
Shilei Jin ◽  
Jianyi Zhou ◽  
Lei Zhang
Keyword(s):  
Power Amplifier ◽  
High Performance ◽  
High Efficiency ◽  
Control Circuit ◽  
Defected Ground Structure ◽  
Ground Structure ◽  
Power Added Efficiency ◽  
Harmonic Control ◽  
Resonance Frequencies ◽  
Class F

In this article, the development of a high-efficiency power amplifier (PA) with the inverse class-F configuration and a novel 3/4 spiral defected ground structure (DGS) is presented. The proposed DGS structure has improved rejection characteristic and its resonance frequencies are more convenient to adjust than conventional symmetric and asymmetric spiral structure. The electromagnetic-simulated result shows that the proposed circuit has improved harmonic control performance with simplified structure and less return loss than the conventional microstrip harmonic control circuit. The 3/4 spiral harmonics control circuit (HCC) can be modeled by three parallel RLC resonators. Using the proposed structure a high-performance harmonic control circuit is designed for implementing an inverse class-F PA. For comparison, two inverse class-F PAs operating at 2.4 GHz have been implemented by the microstrip HCC and the proposed HCC, respectively. According to the experiment results, the size of the proposed inverse class-F PA is reduced by 20%, the power-added efficiency and the gain are increased by 4.8% and 1.5 dB, respectively.

scholarly journals A 6 GHz Integrated High-Efficiency Class-F−1 Power Amplifier in 65 nm CMOS Achieving 47.8% Peak PAE

Electronics ◽  
2021 ◽  
Vol 10 (20) ◽  
pp. 2450
Author(s):  
Syed Muhammad Ammar Ali ◽  
S. M. Rezaul Hasan
Keyword(s):  
Power Amplifier ◽  
Peak Power ◽  
High Efficiency ◽  
Impedance Matching ◽  
Center Frequency ◽  
Dual Purpose ◽  
Power Added Efficiency ◽  
Harmonic Control ◽  
Saturated Output Power ◽  
Class F

This paper reports a “single-transistor” Class-F−1 power amplifier (PA) in 65 nm CMOS, which operates at the microwave center frequency of 6 GHz. The PA is loaded with a Class-F−1 harmonic control network, employing a new “parasitic-aware” topology deduced using a novel iterative algorithm. A dual-purpose output matching network is designed, which not only serves the purpose of output impedance matching, but also reinforces the harmonic control of the Class-F−1 harmonic network. This proposed PA yields a peak power-added efficiency (PAE) of 47.8%, which is one of the highest when compared to previously reported integrated microwave/millimeter-wave PAs in CMOS and SiGe technologies. The amplifier shows a saturated output power of 14.4 dBm along with an overall gain of 13.8 dB.

scholarly journals A 2.5-GHz 1-V High Efficiency CMOS Power Amplifier IC with a Dual-Switching Transistor and Third Harmonic Tuning Technique

Electronics ◽  
2019 ◽  
Vol 8 (1) ◽  
pp. 69 ◽  
Author(s):  
Taufiq Alif Kurniawan ◽  
Toshihiko Yoshimasu
Keyword(s):  
Power Amplifier ◽  
High Efficiency ◽  
Low Voltage ◽  
Supply Voltage ◽  
Drain Current ◽  
Cmos Technology ◽  
Back Gate ◽  
Third Harmonic ◽  
Power Added Efficiency ◽  
Switching Transistor

This paper presents a 2.5-GHz low-voltage, high-efficiency CMOS power amplifier (PA) IC in 0.18-µm CMOS technology. The combination of a dual-switching transistor (DST) and a third harmonic tuning technique is proposed. The DST effectively improves the gain at the saturation power region when the additional gain extension of the secondary switching transistor compensates for the gain compression of the primary one. To achieve high-efficiency performance, the third harmonic tuning circuit is connected in parallel to the output load. Therefore, the flattened drain current and voltage waveforms are generated, which in turn reduce the overlapping and the dc power consumption significantly. In addition, a 0.5-V back-gate voltage is applied to the primary switching transistor to realize the low-voltage operation. At 1 V of supply voltage, the proposed PA has achieved a power added efficiency (PAE) of 34.5% and a saturated output power of 10.1 dBm.

scholarly journals X-Band High-Efficiency Continuous Class B Power Amplifier GaN MMIC Assisted by Input Second-Harmonic Tuning

Electronics ◽  
2019 ◽  
Vol 8 (11) ◽  
pp. 1312 ◽  
Author(s):  
Chen Jin ◽  
Yuan Gao ◽  
Wei Chen ◽  
Jianhua Huang ◽  
Zhiyu Wang ◽  
...  
Keyword(s):  
Power Amplifier ◽  
Integrated Circuit ◽  
High Efficiency ◽  
Second Harmonic ◽  
Power Added Efficiency ◽  
Optimum Load ◽  
Measurement Results ◽  
Class B ◽  
Point To Point ◽  
Output Capacitance

This paper presents a high-efficiency continuous class B power amplifier MMIC (Monolithic Microwave Integrated Circuit) from 8 GHz to 10.5 GHz, fabricated with 0.25 μm GaN-on-SiC technology. The Pedro load-line method was performed to calculate the optimum load of the GaN field-effect transistor (FET) for efficiency enhancement. Optimized by an output second-harmonic tuned network, fundamental to second-harmonic impedance, mapping was established point-to-point within a broad frequency band, which approached the classic continuous class B mode with an expanded high-efficiency bandwidth. Moreover, the contribution to the output capacitance of the FET was introduced into the output second-harmonic tuned network, which simplified the structure of the output matching network. Assisted by the second-harmonic source-pull technique, the input second-harmonic tuned network was optimized to improve the efficiency of the power amplifier over the operation band. The measurement results showed 51–59% PAE (Power Added Efficiency) and 19.8–21.2 dB power gain with a saturated power of 40.8–42.2 dBm from 8 GHz to 10.5 GHz. The size of the chip was 3.2 × 2.4 mm2.

Concurrent dual band class F power amplifier with novel harmonic control network

2012 ◽  
Vol 54 (3) ◽  
pp. 707-711 ◽  
Author(s):  
Yao Ding ◽  
Yong-Xin Guo ◽  
Fa-Lin Liu ◽  
Lan You
Keyword(s):  
Power Amplifier ◽  
Dual Band ◽  
Control Network ◽  
Harmonic Control ◽  
Band Class ◽  
Class F

A 3.1-GHz Class-F Power Amplifier With 82% Power-Added-Efficiency

2013 ◽  
Vol 23 (8) ◽  
pp. 436-438 ◽  
Author(s):  
Kenle Chen ◽  
Dimitrios Peroulis
Keyword(s):  
Power Amplifier ◽  
Power Added Efficiency ◽  
Class F

scholarly journals Optimization Technique for High-Gain CMOS Power Amplifier for 5G Applications

2021 ◽  
Vol 11 (24) ◽  
pp. 11691
Author(s):  
Hayeon Jeong ◽  
Huidong Lee ◽  
Bonghyuk Park ◽  
Seunghyun Jang ◽  
Sunwoo Kong ◽  
...  
Keyword(s):  
Power Amplifier ◽  
Optimization Technique ◽  
High Gain ◽  
Common Source ◽  
Power Added Efficiency ◽  
Power Cell ◽  
Measurement Results ◽  
Saturated Output Power ◽  
The Stability ◽  
Parasitic Components

In this study, a differential power amplifier (PA) with a high gain of over 30 dB by configuring a three-stage common source unit amplifier was designed. To ensure the stability of the high-gain differential PA, the analysis to apply the capacitive neutralization method to the differential common source PA was conducted. From the analysis, the required neutralized capacitance was quantitatively calculated from the estimated parasitic components of a power cell used in the PA. To verify the feasibility of the proposed optimization technique, a Ka-band PA was designed with a 65 nm RFCMOS process. The measurement results showed a gain of 30.7 dB. The saturated output power was measured as 16.1 dBm, maximum power-added efficiency (PAE) was 29.7%, and P1dB was 13.1 dBm.

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