Abstraction NBTI model

2021 ◽  
Vol 0 (0) ◽  
Author(s):  
Stephan Adolf ◽  
Wolfgang Nebel
Keyword(s):  
State Space ◽  
Threshold Voltage ◽  
Stress Conditions ◽  
Negative Bias ◽  
Aging Effects ◽  
State Transformation ◽  
Negative Bias Temperature Instability ◽  
Design Time ◽  
Bias Temperature Instability ◽  
Traditional Approaches

Abstract Negative Bias Temperature Instability (NBTI) is one of the major transistor aging effects, possibly leading to timing failures during run-time of a system. Thus one is interested in predicting this effect during design time. In this work an Abstraction NBTI model is introduced reducing the state space of trap-based NBTI models using two abstraction parameters, applying a state transformation to incorporate variable stress conditions. This transformation is faster than traditional approaches. Currently the conversion into estimated threshold voltage damages is a very time consuming process.

A Modified Architecture for Radix-4 Booth Multiplier with Adaptive Hold Logic

2016 ◽  
Vol 4 (1) ◽  
pp. 01-05
Author(s):  
S Suvarna ◽  
K Rajesh ◽  
T Radhu
Keyword(s):  
Threshold Voltage ◽  
High Speed ◽  
Negative Bias ◽  
Positive Bias ◽  
Negative Bias Temperature Instability ◽  
Discrete Cosine Transforms ◽  
Temperature Instability ◽  
Booth Multiplier ◽  
Bias Temperature Instability ◽  
Digital Multipliers

High speed digital multipliers are most efficiently used in many applications such as Fourier transform, discrete cosine transforms, and digital filtering. The throughput of the multipliers is based on speed of the multiplier, and then the entire performance of the circuit depends on it. The pMOS transistor in negative bias cause negative bias temperature instability (NBTI), which increases the threshold voltage of the transistor and reduces the multiplier speed. Similarly, the nMOS transistor in positive bias cause positive bias temperature instability (PBTI).These effects reduce the transistor speed and the system may fail due to timing violations. So here a new multiplier was designed with novel adaptive hold logic (AHL) using Radix-4 Modified Booth Multiplier. By using Radix-4 Modified Booth Encoding (MBE), we can reduce the number of partial products by half. Modified booth multiplier helps to provide higher throughput with low power consumption. This can adjust the AHL circuit to reduce the performance degradation. The expected result will be reduce threshold voltage, increase throughput and speed and also reduce power. This modified multiplier design is coded by Verilog and simulated using Xilinx ISE 12.1 and implemented in Spartan 3E FPGA kit.

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