A 6-bit Low-Power High-Speed Flash ADC using 180 nm CMOS process

In this paper we present a design of Flash-ADC that can achieve high performance and low power consumption. By using the Double Sampling Rate technique and a new comparator topology with low kick-back noise, this design can achieve high sampling rate while still consuming low power. The design is implemented in a 0.18 m CMOS process. The simulation results show that this design can work at 400 MSps and power consumption is only 16.24 mW. The DNL and INL are 0.15 LSB and 0.6 LSB, respectively.

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Ultracompact and low-power-consumption silicon thermo-optic switch for high-speed data

Nanophotonics ◽

10.1515/nanoph-2020-0496 ◽

2020 ◽

Vol 10 (2) ◽

pp. 937-945

Author(s):

Ruihuan Zhang ◽

Yu He ◽

Yong Zhang ◽

Shaohua An ◽

Qingming Zhu ◽

...

Keyword(s):

Power Consumption ◽

Low Power ◽

High Speed ◽

High Performance ◽

Pulse Amplitude ◽

Telecommunication Networks ◽

Low Power Consumption ◽

Power Efficient ◽

High Speed Data ◽

On Chip

AbstractUltracompact and low-power-consumption optical switches are desired for high-performance telecommunication networks and data centers. Here, we demonstrate an on-chip power-efficient 2 × 2 thermo-optic switch unit by using a suspended photonic crystal nanobeam structure. A submilliwatt switching power of 0.15 mW is obtained with a tuning efficiency of 7.71 nm/mW in a compact footprint of 60 μm × 16 μm. The bandwidth of the switch is properly designed for a four-level pulse amplitude modulation signal with a 124 Gb/s raw data rate. To the best of our knowledge, the proposed switch is the most power-efficient resonator-based thermo-optic switch unit with the highest tuning efficiency and data ever reported.

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A NOVEL SWITCHED-CURRENT SUCCESSIVE APPROXIMATION ADC

Journal of Circuits System and Computers ◽

10.1142/s0218126611007049 ◽

2011 ◽

Vol 20 (01) ◽

pp. 15-27 ◽

Cited By ~ 5

Author(s):

XIAN TANG ◽

KONG PANG PUN

Keyword(s):

Power Consumption ◽

Low Power ◽

Successive Approximation ◽

High Speed ◽

High Accuracy ◽

Low Power Consumption ◽

Cmos Process ◽

Power Efficient ◽

Successive Approximation Adc ◽

Switched Current

A novel switched-current successive approximation ADC is presented in this paper with high speed and low power consumption. The proposed ADC contains a new high-accuracy and power-efficient switched-current S/H circuit and a speed-improved current comparator. Designed and simulated in a 0.18-μm CMOS process, this 8-bit ADC achieves 46.23 dB SNDR at 1.23 MS/s consuming 73.19 μW under 1.2 V voltage supply, resulting in an ENOB of 7.38-bit and an FOM of 0.357 pJ/Conv.-step.

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Low-power consumption seamless wireless and wired links using transparent waveform transfer

Advanced Optical Technologies ◽

10.1515/aot-2014-0050 ◽

2014 ◽

Vol 3 (5-6) ◽

Author(s):

Tetsuya Kawanishi

Keyword(s):

Power Consumption ◽

Optical Fiber ◽

Low Power ◽

Millimeter Wave ◽

Optical Fibers ◽

High Speed ◽

High Performance ◽

Digital Signal ◽

Low Power Consumption ◽

Wireless Links

AbstractThis paper describes wired and wireless seamless networks consisting of radiowave and optical fiber links. Digital coherent technology developed for high-speed optical fiber transmission can mitigate signal deformation in radiowave links in the air as well as in optical fibers. Radio-over-fiber (RoF) technique, which transmits radio waveforms on intensity envelops of optical signals, can provide direct waveform transfer between optical and radio signals by using optical-to-electric or electric-to-optical conversion devices. Combination of RoF in millimeter-wave bands and digital coherent with high-performance digital signal processing (DSP) can provide wired and wireless seamless links where bit rate of wireless links would be close to 100 Gb/s. Millimeter-wave transmission distance would be shorter than a few kilometers due to large atmospheric attenuation, so that many moderate distance wireless links, which are seamlessly connected to optical fiber networks should be required to provide high-speed mobile-capable networks. In such systems, reduction of power consumption at media converters connecting wired and wireless links would be very important to pursue both low-power consumption and large capacity.

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A Novel CNFET Technology Based 3 Bit Flash ADC for Low-Voltage High Speed SoC Application

International Journal of Engineering Research in Africa ◽

10.4028/www.scientific.net/jera.19.19 ◽

2015 ◽

Vol 19 ◽

pp. 19-36 ◽

Cited By ~ 2

Author(s):

P.A. Gowri Sankar ◽

G. Sathiyabama

Keyword(s):

Power Consumption ◽

Low Power ◽

Circuit Design ◽

Field Effect ◽

High Speed ◽

Low Voltage ◽

Supply Voltage ◽

Cmos Technology ◽

Flash Adc ◽

Simulation Results

The continuous scaling down of metal-oxide-semiconductor field effect transistors (MOSFETs) led to the considerable impact in the analog-digital mixed signal integrated circuit design for system-on-chips (SoCs) application. SoCs trends force ADCs to be integrated on the chip with other digital circuits. These trends present new challenges in ADC circuit design based on existing CMOS technology. In this paper, we have designed and analyzed a 3-bit high speed, low-voltage and low-power flash ADC at 32nm CNFET technology for SoC applications. The proposed ADC utilizes the Threshold Inverter Quantization (TIQ) technique that uses two cascaded carbon nanotube field effect transistor (CNFET) inverters as a comparator. The TIQ technique proposed has been developed for better implementation in SoC applications. The performance of the proposed ADC is studied using two different types of encoders such as ROM and Fat tree encoders. The proposed ADCs circuits are simulated using Synopsys HSPICE with standard 32nm CNFET model at 0.9 input supply voltage. The simulation results show that the proposed 3 bit TIQ technique based flash ADC with fat tree encoder operates up to 8 giga samples per second (GSPS) with 35.88µW power consumption. From the simulation results, we observed that the proposed TIQ flash ADC achieves high speed, small size, low power consumption, and low voltage operation compared to other low power CMOS technology based flash ADCs. The proposed method is sensitive to process, temperature and power supply voltage variations and their impact on the ADC performance is also investigated.

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High Speed and Low Power Consumption by Exploitation using Novel XOR and XNOR Gates

International Journal of Innovative Technology and Exploring Engineering - Special Issue ◽

10.35940/ijitee.k1321.10812s19 ◽

2019 ◽

Vol 8 (12S) ◽

pp. 1182-1186

Keyword(s):

Power Consumption ◽

Low Power ◽

High Speed ◽

Short Circuit ◽

Full Adder ◽

Low Power Consumption ◽

Cmos Process ◽

Input Noise ◽

Threshold Voltages ◽

Output Capacitance

The present paper proposes a high speed and low power consumption by travelling novel XOR and XNOR gates. The present circuit consist optimized power intakeas well asdelay due to smallamount produced capacitance and power dissipation for low short circuit. Here we utilize 6 new hybrid 1 bit full adder circuitthat produces to and fro XOR/XNOR gates. Here the present circuit has its own advantages like rapidity, power consumption and delay in power product, dynamic capability and so on. Here we proposed signals like HSPICE, Cadence simulations for investigating the performance results which are based on 65-nm CMOS process technical models that indicate high speed and power against FA signals. So here we propose a novel new transistor sizing method that optimizes the PDP circuits. The present circuit investigates on various supply terms of variations like threshold voltages, size of transistors, input noise and output capacitance by utilizing numerical computation particle swam optimization algorithm for achieving desired value in optimum PDP with few iterations

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A Low-Power 12-Bit 20 MS/s Asynchronously Controlled SAR ADC for WAVE ITS Sensor Based Applications

Sensors ◽

10.3390/s21072260 ◽

2021 ◽

Vol 21 (7) ◽

pp. 2260

Author(s):

Khuram Shehzad ◽

Deeksha Verma ◽

Danial Khan ◽

Qurat Ul Ain ◽

Muhammad Basim ◽

...

Keyword(s):

Power Consumption ◽

Low Power ◽

High Speed ◽

Intelligent Transportation System ◽

Cmos Process ◽

Process Technology ◽

Back Issue ◽

Digital To Analog Converter ◽

Analog To Digital ◽

Switching Method

A low power 12-bit, 20 MS/s asynchronously controlled successive approximation register (SAR) analog-to-digital converter (ADC) to be used in wireless access for vehicular environment (WAVE) intelligent transportation system (ITS) sensor based application is presented in this paper. To optimize the architecture with respect to power consumption and performance, several techniques are proposed. A switching method which employs the common mode charge recovery (CMCR) switching process is presented for capacitive digital-to-analog converter (CDAC) part to lower the switching energy. The switching technique proposed in our work consumes 56.3% less energy in comparison with conventional CMCR switching method. For high speed operation with low power consumption and to overcome the kick back issue in the comparator part, a mutated dynamic-latch comparator with cascode is implemented. In addition, to optimize the flexibility relating to the performance of logic part, an asynchronous topology is employed. The structure is fabricated in 65 nm CMOS process technology with an active area of 0.14 mm2. With a sampling frequency of 20 MS/s, the proposed architecture attains signal-to-noise distortion ratio (SNDR) of 65.44 dB at Nyquist frequency while consuming only 472.2 µW with 1 V power supply.

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LOW-POWER, PARALLEL INTERFACE WITH CONTINUOUS-TIME ADAPTIVE PASSIVE EQUALIZER AND CROSSTALK CANCELLATION

International Journal of High Speed Electronics and Systems ◽

10.1142/s0129156405003260 ◽

2005 ◽

Vol 15 (02) ◽

pp. 459-476

Author(s):

C. PATRICK YUE ◽

JAEJIN PARK ◽

RUIFENG SUN ◽

L. RICK CARLEY ◽

FRANK O'MAHONY

Keyword(s):

Low Power ◽

Electromagnetic Interference ◽

Continuous Time ◽

High Speed ◽

High Performance ◽

Process Variations ◽

Cmos Process ◽

Power Circuit ◽

Crosstalk Cancellation ◽

Circuit Components

This paper presents the low-power circuit techniques suitable for high-speed digital parallel interfaces each operating at over 10 Gbps. One potential application for such high-performance I/Os is the interface between the channel IC and the magnetic read head in future compact hard disk systems. First, a crosstalk cancellation technique using a novel data encoding scheme is introduced to suppress electromagnetic interference (EMI) generated by the adjacent parallel I/Os . This technique is implemented utilizing a novel 8-4-PAM signaling with a data look-ahead algorithm. The key circuit components in the high-speed interface transceiver including the receive sampler, the phase interpolator, and the transmitter output driver are described in detail. Designed in a 0.13-μm digital CMOS process, the transceiver consumes 310 mW per 10-Gps channel from a I-V supply based on simulation results. Next, a 20-Gbps continuous-time adaptive passive equalizer utilizing on-chip lumped RLC components is described. Passive equalizers offer the advantages of higher bandwidth and lower power consumption compared with conventional designs using active filter. A low-power, continuous-time servo loop is designed to automatically adjust the equalizer frequency response for the optimal gain compensation. The equalizer not only adapts to different channel characteristics, but also accommodates temperature and process variations. Implemented in a 0.25-μm, 1P6M BiCMOS process, the equalizer can compensate up to 20 dB of loss at 10 GHz while only consumes 32 mW from a 2.5-V supply.

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A LOW-POWER AND HIGH-SPEED D FLIP-FLOP USING A SINGLE LATCH

Journal of Circuits System and Computers ◽

10.1142/s0218126602000239 ◽

2002 ◽

Vol 11 (01) ◽

pp. 51-55

Author(s):

ROBERT C. CHANG ◽

L.-C. HSU ◽

M.-C. SUN

Keyword(s):

Power Consumption ◽

Low Power ◽

Power Dissipation ◽

High Speed ◽

Operating Frequency ◽

Flip Flop ◽

Lower Power ◽

Simulation Results ◽

Hspice Simulation

A novel low-power and high-speed D flip-flop is presented in this letter. The flip-flop consists of a single low-power latch, which is controlled by a positive narrow pulse. Hence, fewer transistors are used and lower power consumption is achieved. HSPICE simulation results show that power dissipation of the proposed D flip-flop has been reduced up to 76%. The operating frequency of the flip-flop is also greatly increased.

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