Improving embedded Flash memory technology: silicon and metal nanocrystals, engineered charge-trapping layers and split-gate memory architectures

AbstractAlthough conventional floating gate (FG) Flash memory has already gone into the sub-30 nm node, the technology challenges are formidable beyond 20nm. The fundamental challenges include FG interference, few-electron storage caused statistical fluctuation, poor short-channel effect, WL-WL breakdown, poor reliability, and edge effect sensitivity. Although charge-trapping (CT) devices have been proposed very early and studied for many years, these devices have not prevailed over FG Flash in the > 30nm node. However, beyond 20nm the advantage of CT devices may become more significant. Especially, due to the simpler structure and no need for charge storage isolation, CT is much more desirable than FG in 3D stackable Flash memory. Optimistically, 3D CT Flash memory may allow the Moore's law to continue for at least another decade. In this paper, we review the operation principles of CT devices and several variations such as MANOS and BE-SONOS. We will then discuss 3D memory architectures including the bit-cost scalable approach. Technology challenges and the poly-silicon thin film transistor (TFT) issues will be addressed in detail.

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A Vertical Split-Gate Flash Memory Featuring High-Speed Source-Side Injection Programming, Read Disturb Free, and 100K Endurance for Embedded Flash (eFlash) Scaling and Computing-In-Memory (CIM)

2020 IEEE International Electron Devices Meeting (IEDM) ◽

10.1109/iedm13553.2020.9372036 ◽

2020 ◽

Author(s):

Tzu-Hsuan Hsu ◽

Hang-Ting Lue ◽

Po-Kai Hsu ◽

Teng-Hao Yeh ◽

Pei-Ying Du ◽

...

Keyword(s):

Flash Memory ◽

High Speed ◽

Embedded Flash

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Flash memory based on solution processed hafnium dioxide charge trapping layer

Journal of Materials Chemistry C ◽

10.1039/c4tc00010b ◽

2014 ◽

Vol 2 (21) ◽

pp. 4233-4238 ◽

Cited By ~ 9

Author(s):

Jiaqing Zhuang ◽

Su-Ting Han ◽

Ye Zhou ◽

V. A. L. Roy

Keyword(s):

Flash Memory ◽

Sol Gel ◽

Charge Trapping ◽

Hafnium Dioxide ◽

Solution Processed ◽

Gel Technique ◽

A Charge

Hafnium dioxide (HfO2) film prepared by the sol–gel technique has been used as a charge trapping layer in organic flash memory.

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Enhanced Programming and Erasing Speeds in P-Channel Charge-Trapping Flash Memory Device With SiGe Buried Channel

IEEE Electron Device Letters ◽

10.1109/led.2012.2206069 ◽

2012 ◽

Vol 33 (9) ◽

pp. 1264-1266 ◽

Cited By ~ 8

Author(s):

Li-Jung Liu ◽

Kuei-Shu Chang-Liao ◽

Yi-Chuen Jian ◽

Jen-Wei Cheng ◽

Tien-Ko Wang ◽

...

Keyword(s):

Flash Memory ◽

Charge Trapping ◽

Memory Device ◽

Buried Channel

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Temperature-Dependent Physical and Memory Characteristics of Atomic-Layer-DepositedRuOxMetal Nanocrystal Capacitors

Journal of Nanomaterials ◽

10.1155/2011/810879 ◽

2011 ◽

Vol 2011 ◽

pp. 1-12 ◽

Cited By ~ 6

Author(s):

S. Maikap ◽

W. Banerjee ◽

T. C. Tien ◽

T. Y. Wang ◽

J. R. Yang

Keyword(s):

Gate Voltage ◽

Annealing Temperature ◽

Deep Level ◽

Charge Trapping ◽

Atomic Layer ◽

Memory Window ◽

Silicate Layer ◽

Metal Nanocrystals ◽

Annealing Temperatures ◽

Memory Characteristics

Physical and memory characteristics of the atomic-layer-depositedRuOxmetal nanocrystal capacitors in an n-Si/SiO2/HfO2/RuOx/Al2O3/Pt structure with different postdeposition annealing temperatures from 850–1000°C have been investigated. TheRuOxmetal nanocrystals with an average diameter of 7 nm and a highdensity of 0.7 × 1012/cm2are observed by high-resolution transmission electron microscopy after a postdeposition annealing temperature at 1000°C. The density ofRuOxnanocrystal is decreased (slightly) by increasing the annealing temperatures, due to agglomeration of multiple nanocrystals. The RuO3nanocrystals and Hf-silicate layer at the SiO2/HfO2interface are confirmed by X-ray photoelectron spectroscopy. For post-deposition annealing temperature of 1000°C, the memory capacitors with a small equivalent oxide thickness of ~9 nm possess a large hysteresis memory window of >5 V at a small sweeping gate voltage of ±5 V. A promising memory window under a small sweeping gate voltage of ~3 V is also observed due to charge trapping in theRuOxmetal nanocrystals. The program/erase mechanism is modified Fowler-Nordheim (F-N) tunneling of the electrons and holes from Si substrate. The electrons and holes are trapped in theRuOxnanocrystals. Excellent program/erase endurance of 106cycles and a large memory window of 4.3 V with a small charge loss of ~23% at 85°C are observed after 10 years of data retention time, due to the deep-level traps in theRuOxnanocrystals. The memory structure is very promising for future nanoscale nonvolatile memory applications.

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Second-Bit-Effect-Free Multibit-Cell Flash Memory Using $\hbox{Si}_{3} \hbox{N}_{4}/\hbox{ZrO}_{2}$ Split Charge Trapping Layer

IEEE Transactions on Electron Devices ◽

10.1109/ted.2009.2026090 ◽

2009 ◽

Vol 56 (9) ◽

pp. 1966-1973 ◽

Cited By ~ 1

Author(s):

Gang Zhang ◽

Seung-Hwan Lee ◽

Chang Ho Ra ◽

Hua-Min Li ◽

Won Jong Yoo

Keyword(s):

Flash Memory ◽

Charge Trapping

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Nb2O5 and Ti-Doped Nb2O5 Charge Trapping Nano-Layers Applied in Flash Memory

Nanomaterials ◽

10.3390/nano8100799 ◽

2018 ◽

Vol 8 (10) ◽

pp. 799 ◽

Cited By ~ 1

Author(s):

Jer Wang ◽

Chyuan Kao ◽

Chien Wu ◽

Chun Lin ◽

Chih Lin

Keyword(s):

Flash Memory ◽

Charge Trapping ◽

Memory Device ◽

Dielectric Constants ◽

Oxide Semiconductor ◽

Flat Band ◽

Hysteresis Curve ◽

Band Shift ◽

K Value ◽

High K

High-k material charge trapping nano-layers in flash memory applications have faster program/erase speeds and better data retention because of larger conduction band offsets and higher dielectric constants. In addition, Ti-doped high-k materials can improve memory device performance, such as leakage current reduction, k-value enhancement, and breakdown voltage increase. In this study, the structural and electrical properties of different annealing temperatures on the Nb2O5 and Ti-doped Nb2O5(TiNb2O7) materials used as charge-trapping nano-layers in metal-oxide-high k-oxide-semiconductor (MOHOS)-type memory were investigated using X-ray diffraction (XRD) and atomic force microscopy (AFM). Analysis of the C-V hysteresis curve shows that the flat-band shift (∆VFB) window of the TiNb2O7 charge-trapping nano-layer in a memory device can reach as high as 6.06 V. The larger memory window of the TiNb2O7 nano-layer is because of a better electrical and structural performance, compared to the Nb2O5 nano-layer.

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