Polysilicon–Oxide–Nitride–Oxide–Silicon-Type Flash Memory Using an Y[sub 2]O[sub 3] Film as a Charge Trapping Layer

2008 ◽  
Vol 11 (7) ◽  
pp. G37 ◽  
Author(s):  
Tung-Ming Pan ◽  
Wen-Wei Yeh
Keyword(s):  
Flash Memory ◽  
Charge Trapping ◽  
A Charge ◽  
Nitride Oxide

Flash memory based on solution processed hafnium dioxide charge trapping layer

2014 ◽  
Vol 2 (21) ◽  
pp. 4233-4238 ◽  
Author(s):  
Jiaqing Zhuang ◽  
Su-Ting Han ◽  
Ye Zhou ◽  
V. A. L. Roy
Keyword(s):  
Flash Memory ◽  
Sol Gel ◽  
Charge Trapping ◽  
Hafnium Dioxide ◽  
Solution Processed ◽  
Gel Technique ◽  
A Charge

Hafnium dioxide (HfO2) film prepared by the sol–gel technique has been used as a charge trapping layer in organic flash memory.

scholarly journals Chemical-Vapor-Deposited Graphene as Charge Storage Layer in Flash Memory Device

2016 ◽  
Vol 2016 ◽  
pp. 1-6 ◽  
Author(s):  
W. J. Liu ◽  
L. Chen ◽  
P. Zhou ◽  
Q. Q. Sun ◽  
H. L. Lu ◽  
...  
Keyword(s):  
Flash Memory ◽  
Room Temperature ◽  
Metal Layer ◽  
Chemical Vapor ◽  
Charge Trapping ◽  
Memory Device ◽  
Water Molecules ◽  
Oh Groups ◽  
Chemical Vapor Deposited ◽  
A Charge

We demonstrated a flash memory device with chemical-vapor-deposited graphene as a charge trapping layer. It was found that the average RMS roughness of block oxide on graphene storage layer can be significantly reduced from 5.9 nm to 0.5 nm by inserting a seed metal layer, which was verified by AFM measurements. The memory window is 5.6 V for a dual sweep of ±12 V at room temperature. Moreover, a reduced hysteresis at the low temperature was observed, indicative of water molecules or −OH groups between graphene and dielectric playing an important role in memory windows.

Silicon-oxide-nitride-oxide-silicon-type flash memory with a high-k NdTiO3 charge trapping layer

2008 ◽  
Vol 92 (11) ◽  
pp. 112906 ◽  
Author(s):  
Tung-Ming Pan ◽  
Te-Yi Yu
Keyword(s):  
Flash Memory ◽  
Silicon Oxide ◽  
Charge Trapping ◽  
High K ◽  
Nitride Oxide

High-speed and low-voltage performance in a charge-trapping flash memory using a NiO tunnel junction

2011 ◽  
Vol 44 (15) ◽  
pp. 155105 ◽  
Author(s):  
Yujeong Seo ◽  
Ho-Myoung An ◽  
Hee-Dong Kim ◽  
In Rok Hwang ◽  
Sa Hwan Hong ◽  
...  
Keyword(s):  
Tunnel Junction ◽  
Flash Memory ◽  
High Speed ◽  
Low Voltage ◽  
Charge Trapping ◽  
Voltage Performance ◽  
A Charge

Engineering of Si-Rich Nitride Charge-Trapping Layer for Highly Reliable Metal–Oxide–Nitride–Oxide–Semiconductor Type NAND Flash Memory with Multi-Level Cell Operation

2012 ◽  
Vol 51 (2R) ◽  
pp. 021103
Author(s):  
Ryota Fujitsuka ◽  
Katsuyuki Sekine ◽  
Akiko Sekihara ◽  
Atsushi Fukumoto ◽  
Junya Fujita ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Flash Memory ◽  
Charge Trapping ◽  
Oxide Semiconductor ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Multi Level ◽  
Nitride Oxide ◽  
Semiconductor Type

Backside Storage Non-Volatile Memories: Ultra-Thin Silicon Layer on a Complex Thin Film Structure

2004 ◽  
Vol 830 ◽  
Author(s):  
H. Silva ◽  
S. Tiwari
Keyword(s):  
Silicon Layer ◽  
Charge Trapping ◽  
Film Structure ◽  
Short Length ◽  
Floating Gate ◽  
Silicon On Insulator ◽  
Substrate Preparation ◽  
Device Structures ◽  
A Charge ◽  
Nitride Oxide

ABSTRACTBackside storage memories present an alternative to the conventional front-floating gate geometries by storing charge in defects on the back of a thin depleted silicon channel. This paper focuses on the fabrication of these devices using a modified Smart-Cut™ substrate preparation process followed by standard CMOS processing. The substrate is a complex silicon-on-insulator (SOI) substrate where instead of the buried oxide alone a charge trapping multi-layer stack of oxide-nitride-oxide (ONO) is used as the buried insulator. We demonstrate here the operation of these device structures at ultra-short length scales and summarize the characteristics of their operation.

scholarly journals Investigation of Intra-Nitride Charge Migration Suppression in SONOS Flash Memory

Micromachines ◽  
2019 ◽  
Vol 10 (6) ◽  
pp. 356 ◽  
Author(s):  
Seung-Dong Yang ◽  
Jun-Kyo Jung ◽  
Jae-Gab Lim ◽  
Seong-gye Park ◽  
Hi-Deok Lee ◽  
...  
Keyword(s):  
Silicon Nitride ◽  
Photoelectron Spectroscopy ◽  
Flash Memory ◽  
Silicon Oxide ◽  
Charge Trapping ◽  
Charge Migration ◽  
Charge Loss ◽  
Capacitance Voltage ◽  
Nitride Oxide ◽  
N2 Plasma

In order to suppress the intra-nitride charge spreading in 3D Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) flash memory where the charge trapping layer silicon nitride is shared along the cell string, N2 plasma treated on the silicon nitride is proposed. Experimental results show that the charge loss decreased in the plasma treated device after baking at 300 °C for 2 h. To extract trap density according to the location in the trapping layer, capacitance-voltage analysis was used and N2 plasma treatment was shown to be effective to restrain the interface trap formation between blocking oxide and silicon nitride. Moreover, from X-ray Photoelectron Spectroscopy, the reduction of Si-O-N bonding was observed.

scholarly journals Retention Enhancement in Low Power NOR Flash Array with High-κ–Based Charge-Trapping Memory by Utilizing High Permittivity and High Bandgap of Aluminum Oxide

Micromachines ◽  
2021 ◽  
Vol 12 (3) ◽  
pp. 328
Author(s):  
Young Suh Song ◽  
Byung-Gook Park
Keyword(s):  
Aluminum Oxide ◽  
Flash Memory ◽  
Computer Aided Design ◽  
Charge Trapping ◽  
Device Structure ◽  
Retention Characteristics ◽  
Charge Trapping Memory ◽  
A Charge ◽  
Aided Design ◽  
Nor Flash

For improving retention characteristics in the NOR flash array, aluminum oxide (Al2O3, alumina) is utilized and incorporated as a tunneling layer. The proposed tunneling layers consist of SiO2/Al2O3/SiO2, which take advantage of higher permittivity and higher bandgap of Al2O3 compared to SiO2 and silicon nitride (Si3N4). By adopting the proposed tunneling layers in the NOR flash array, the threshold voltage window after 10 years from programming and erasing (P/E) was improved from 0.57 V to 4.57 V. In order to validate our proposed device structure, it is compared to another stacked-engineered structure with SiO2/Si3N4/SiO2 tunneling layers through technology computer-aided design (TCAD) simulation. In addition, to verify that our proposed structure is suitable for NOR flash array, disturbance issues are also carefully investigated. As a result, it has been demonstrated that the proposed structure can be successfully applied in NOR flash memory with significant retention improvement. Consequently, the possibility of utilizing HfO2 as a charge-trapping layer in NOR flash application is opened.

Engineering of Si-Rich Nitride Charge-Trapping Layer for Highly Reliable Metal–Oxide–Nitride–Oxide–Semiconductor Type NAND Flash Memory with Multi-Level Cell Operation

2012 ◽  
Vol 51 ◽  
pp. 021103 ◽  
Author(s):  
Ryota Fujitsuka ◽  
Katsuyuki Sekine ◽  
Akiko Sekihara ◽  
Atsushi Fukumoto ◽  
Junya Fujita ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Flash Memory ◽  
Charge Trapping ◽  
Oxide Semiconductor ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Multi Level ◽  
Nitride Oxide ◽  
Semiconductor Type

SONOS-type flash memory using an HfO/sub 2/ as a charge trapping layer deposited by the sol-gel spin-coating method

2006 ◽  
Vol 27 (8) ◽  
pp. 653-655 ◽  
Author(s):  
Hsin-Chiang You ◽  
Tze-Hsiang Hsu ◽  
Fu-Hsiang Ko ◽  
Jiang-Wen Huang ◽  
Wen-Luh Yang ◽  
...  
Keyword(s):  
Flash Memory ◽  
Spin Coating ◽  
Sol Gel ◽  
Charge Trapping ◽  
Spin Coating Method ◽  
Coating Method ◽  
A Charge
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