VLSI Design and Comparison of DA and LMS Based Reconfigurable FIR Filter

2016 ◽  
Vol 5 (2) ◽  
pp. 124
Author(s):  
P. Hemanthkumar ◽  
Y. Sai Kiran ◽  
V. Nava Teja
Keyword(s):  
Performance Metrics ◽  
Finite Impulse Response ◽  
Vlsi Design ◽  
Fir Filter ◽  
Inner Product ◽  
Distributed Arithmetic ◽  
Power Efficient ◽  
Consumption Energy ◽  
The Look ◽  
Suitable Area

<p>Here, we exhibit the design optimization of one- and two-dimensional fully-pipelined computing structures for area-delay-power-efficient implementation of finite impulse response (FIR) filter by systolic decomposition of distributed arithmetic (DA)-based inner-product computation. This plan is found to offer a flexible choice of the address length of the look-up-tables (LUT) for DA-based computation to determine suitable area-time trade-off. It is seen that by using smaller address-lengths for DA-based computing units, it is possible to decrease the memory-size but on the other side that leads to increase of adder complexity and the latency. For efficient DA-based realization of FIR filters of different orders, the flexible linear systolic design is implemented on a Xilinx Virtex-E XCV2000E FPGA using a hybrid combination of Handel-C and parameterizable VHDL cores. Various key performance metrics such as number of slices, maximum usable frequency, dynamic power consumption, energy density and energy throughput are estimated for different filter orders and address-lengths. Obtained results on analysis shows that performance metrics of the proposed implementation is broadly in line with theoretical expectations. We have seen that the choice of address-length M=4 gives the best of area-delay power-efficient realizations of the FIR filter for different filter orders. Moreover, the proposed FPGA implementation is found to involve significantly less area-delay complexity compared with the existing DA-based implementations of FIR filter.</p>

scholarly journals FPGA Based Hardware Co-Simulation of an Area and Power Efficient FIR Filter for Wireless Communication Systems

2010 ◽  
Vol 1 (1) ◽  
pp. 113-122
Author(s):  
Rajesh Kumar ◽  
Swapna Devi ◽  
S.S. Pattnaik
Keyword(s):  
Wireless Communication ◽  
Communication Systems ◽  
Cost Effective ◽  
Fir Filter ◽  
Wireless Communication Systems ◽  
Effective Solution ◽  
Distributed Arithmetic ◽  
Power Efficient ◽  
Look Up Table ◽  
The Look

“In this paper FPGA based hardware co-simulation of an area and power efficient FIR filter for wireless communication systems is presented. The implementation is based on distributed arithmetic (DA) which substitutes multiply-and-accumulate operations with look up table (LUT) accesses. Parallel Distributed arithmetic (PDA) look up table approach is used to implement an FIR Filter taking optimal advantage of the look up table structure of FPGA using VHDL. The proposed design is hardware co-simulated using System Generator10.1, synthesized with Xilinx ISE 10.1 software, and implemented on Virtex-4 based xc4vlx25-10ff668 target device. Results show that the proposed design operates at 17.5 MHz throughput and consumes 0.468W power with considerable reduction in required resources to implement the design as compared to Coregen and add/shift based design styles. Due to this reduction in required resources the proposed design can also be implemented on Spartan-3 FPGA device to provide cost effective solution for DSP and wireless communication applications.”

scholarly journals Design of parallel and pipelined DA based OBC fir filter for software defined radio

2019 ◽  
Vol 14 (3) ◽  
pp. 1228
Author(s):  
Rajmohan Madasamy ◽  
Himanshu Shekhar
Keyword(s):  
Software Defined Radio ◽  
Finite Impulse Response ◽  
New Technology ◽  
Intermediate Frequency ◽  
Fir Filter ◽  
Inner Product ◽  
Distributed Arithmetic ◽  
Binary Coding ◽  
Processing Block ◽  
Address Line

Software Defined Radio (SDR) is a new technology used to implement different wireless communication standard for mobile communication. The Intermediate Frequency (IF) block is the most demanding block in software defined radio. The most important task in intermediate processing block is digital filtering which is carried out by Finite Impulse Response (FIR) filter. One of the major techniques for the calculation of inner product is Distributed Arithmetic (DA) based FIR filter which uses Look Up Table (LUT) to eliminate the need of multiplier. The efficiency of the DA filter is affected with the increasing number of address line and also due to its serial operation. To overcome this problem parallel and pipeline based DA filter using Offset Binary Coding (OBC) for Two Bit At A Time (2-BAAT) is proposed. Our proposed method achieves less area, low power consumption and nominal delay for SDR application.

Low Power Transposed Form 4-Tap Finite Impulse Response Filter using Power Efficient Multiply Accumulate Unit

2021 ◽  
pp. 2250016
Author(s):  
S. Rakesh ◽  
K. S. Vijula Grace
Keyword(s):  
Low Power ◽  
Impulse Response ◽  
Speech Processing ◽  
Video Processing ◽  
Filter Design ◽  
Finite Impulse Response ◽  
Low Power Design ◽  
Fir Filter ◽  
Efficient Design ◽  
Power Efficient

Finite impulse response (FIR) filters find wide application in signal processing applications on account of the stability and linear phase response of the filter. These digital filters are used in applications, like biomedical engineering, wireless communication, image processing, speech processing, digital audio and video processing. Low power design of FIR filter is one of the major constraints that researchers are trying hard to achieve. This paper presents the implementation of a novel power efficient design of a 4-tap 16-bit FIR filter using a modified Vedic multiplier (MVM) and a modified Han Carlson adder (MHCA). The units are coded using Verilog hardware description language and simulated using Xilinx Vivado Design Suite 2015.2. The filter is synthesized for the 7-series Artix field programmable gate array with xc7a100tcsg324-1 as the target device. The proposed filter design showed an improvement of a maximum of 57.44% and a minimum of 2.44% in the power consumption compared to the existing models.

ECG Noise Removal Using Modified Distributed Arithmetic Based Finite Impulse Response Filter

2021 ◽  
Vol 11 (5) ◽  
pp. 1444-1452
Author(s):  
A. Uma ◽  
P. Kalpana
Keyword(s):  
Finite Impulse Response ◽  
Signal To Noise Ratio ◽  
Human Life ◽  
Stress Test ◽  
Noise Removal ◽  
Fir Filter ◽  
Signal Acquisition ◽  
Distributed Arithmetic ◽  
Hardware Resource ◽  
Baseline Wander

ECG monitoring is essential to support human life. During signal acquisition, the signals are contaminated by various noises that occur due to different sources. This paper focuses on Baseline wander and Muscle Artifact noise removal using Distributed Arithmetic (DA) based FIR filters. An area-efficient modified DA based FIR filter consists of LUT-less structure and used for noise removal. The performance of the modified DA based FIR filter is compared with the conventional DA FIR filter. An arbitrary real-time ECG record is taken from MIT-BIH database and Baseline Wander noise, Muscle artifact noises are taken from MIT-BIH noise stress test database. The performance of both filters is evaluated in terms of output Signal to Noise Ratio (SNR) and Mean Square Error (MSE). For Baseline wander noise removal, the modified DA based FIR filter produces high output SNR and also low MSE of 76.6% than the conventional filter. Similarly, for Muscle Artifact noise removal, it produces high SNR, and MSE is reduced to 73.8%. A modified DA based FIR filter is synthesized for the target FPGA device Spartan3E XC3s2000-4fg900 and hardware resource utilization is presented.

scholarly journals HIGH PERFORMANCE ADAPTIVE FINITE IMPULSE RESPONSE FILTER USING NEW DISTRIBUTED ARITHMETIC ALGORITHM

2017 ◽  
Vol 10 (13) ◽  
pp. 352
Author(s):  
Sandeep Kumar ◽  
Vigneswaran T
Keyword(s):  
Parallel Processing ◽  
Low Power ◽  
Impulse Response ◽  
High Speed ◽  
High Performance ◽  
Finite Impulse Response ◽  
Fir Filter ◽  
Distributed Arithmetic ◽  
Power Filter ◽  
Arithmetic Algorithm

Finite Impulse Response (FIR) filters is very important in signal Processing Applications. This research is to analyze the performance of FIR filter with the Xilinx Software. The Distributed Arithmetic (DA) algorithm is extensively used in FIR Filter to improve its speed and reducing the area of the filter. The design of low power filter will be achieved by pipelining and parallel processing concept on distributed Arithmetic. The aim is to design filter which has less delay time and supports the pipelining/parallel processing feature, helps in high speed with less power dissipation and area. The paper discusses FPGA implementation of FIR filter and due to parallel data processing its computation is fast and also provides an efficient architecture in terms of area and power consumption. New Distributed   Arithmetic is a high performance and for low power filter.

LOW POWER VERY LARGE SCALE INTEGRATION (VLSI) DESIGN OF FINITE IMPULSE RESPONSE (FIR) FILTER FOR BIOMEDICAL IMAGING APPLICATION

10.6036/10214 ◽  
2021 ◽  
Vol 96 (5) ◽  
pp. 505-511
Author(s):  
LOGANATHAN MOHANA KANNAN ◽  
DHANASKODI DEEPA
Keyword(s):  
Image Processing ◽  
Biomedical Imaging ◽  
Large Scale ◽  
Filter Design ◽  
Finite Impulse Response ◽  
Vlsi Design ◽  
Fir Filter ◽  
Vedic Multiplier ◽  
Imaging Application ◽  
Processing Techniques

Nowadays, the medical image processing techniques are using Very Large Scale Integrated (VLSI) designs for improving the availability and applicability. The digital filters are important module of Digital Signal Processing (DSP) based systems. Existing Finite Impulse Response (FIR) design approach performed with Partial Full Adder (PFA) based Carry Lookahead Adder (CLA) and parallel prefix adder logic in Vedic multiplier. Objective of this approach is to improve the performance of VLSI circuit by obtaining the result of area, power and delay, also, effective incorporation between VLSI circuit and image processing approach makes improved application availability. The design of high speed digital FIR filter is designed with various adders and multipliers. The incorporation of VLSI design and image processing techniques are used on biomedical imaging applications. The Enhanced FIR filter design utilized the hybrid adder and adaptive Vedic multiplier approaches for increasing the performance of VLSI part and the image processing results are taken from Matrix Laboratory tool. This proposed FIR filter design helps to perform the biomedical imaging techniques. The simulation result obtains the performance of enhanced FIR with area, delay and power; for biomedical imaging, Mean Square Error (MSE) and Peak Signal to Noise Ratio (PSNR) is obtained. Comparing with existing and proposed method, the proposed FIR filter for biomedical imaging application obtains the better result. Thus the design model states with various application availability of VLSI image processing approaches and it obtains the better performance results of both VLSI and image processing applications. Overall, the proposed system is designed by Xilinx ISE 14.5 and the synthesized result is done with ModelSim. Here the biomedical image performance is done by using MATLAB with the adaptation of 2018a. Keywords- Enhanced FIR filter; Adaptive vedic multiplier; Hybrid adder; Biomedical imaging; power delay product;

scholarly journals VLSI Design and Implementation for Adaptive Filter using LMS Algorithm

2012 ◽  
pp. 297-301
Author(s):  
Asit Kumar Subudhi ◽  
Biswajit Mishra ◽  
Mihir N. Mohanty
Keyword(s):  
High Performance ◽  
Adaptive Filters ◽  
Finite Impulse Response ◽  
Vlsi Design ◽  
Digital Signal ◽  
Fir Filter ◽  
Lms Algorithm ◽  
Least Mean Square ◽  
Field Programmable ◽  
Adaptive Noise

Adaptive filters, as part of digital signal systems, have been widely used, as well as in applications such as adaptive noise cancellation, adaptive beam forming, channel equalization, and system identification. However, its implementation takes a great deal and becomes a very important field in digital system world. When FPGA (Field Programmable Logic Array) grows in area and provides a lot of facilities to the designers, it becomes an important competitor in the signal processing market. In general FIR structure has been used more successfully than IIR structure in adaptive filters. However, when the adaptive FIR filter was made this required appropriate algorithm to update the filter’s coefficients. The algorithm used to update the filter coefficient is the Least Mean Square (LMS) algorithm which is known for its simplification, low computational complexity, and better performance in different running environments. When compared to other algorithms used for implementing adaptive filters the LMS algorithm is seen to perform very well in terms of the number of iterations required for convergence. This phenomenon can be achieved by a sufficient choice of bit length to represent the filter’s coefficients. This paper presents a lowcost and high performance programmable digital finite impulse response (FIR) filter. It follows the adaptive algorithm used for the development of the system. The architecture employs the computation sharing algorithm to reduce the computation complexity.

Efficient Parallel Architecture for Fixed-Coefficient and Variable-Coefficient FIR Filters Using Distributed Arithmetic

2016 ◽  
Vol 25 (07) ◽  
pp. 1650073 ◽  
Author(s):  
Subodh Kumar Singhal ◽  
Basant Kumar Mohanty
Keyword(s):  
Variable Coefficient ◽  
Complexity Analysis ◽  
Finite Impulse Response ◽  
Clock Cycle ◽  
Theoretical Estimate ◽  
Parallel Architecture ◽  
Block Size ◽  
Fir Filter ◽  
Distributed Arithmetic ◽  
Filter Length

In this paper, we performed the complexity analysis of fixed-coefficient and variable-coefficient distributed arithmetic (DA)-based finite impulse response (FIR) filter structures to observe the effect of LUT decomposition on the area complexity of DA structure. The complexity analysis reveals that the area complexity of different units of DA FIR filter structure does not increase proportionately with the level of parallelism. An appropriate selection of LUT decomposition factor, and introducing higher level of parallelism in the computation could improve the area-delay efficiency of both fixed-coefficient and variable-coefficient DA-based FIR structures. Based on these findings, we have proposed bit-parallel block-based DA structures, for fixed-coefficient and variable-coefficient FIR. The proposed structures process one block of input samples and produce one block of outputs in every clock cycle. Theoretical estimate shows that the proposed fixed-coefficient structure, for block-size 8 and filter-length 32, involves eight times more ROM-LUT words, eight times more adders, two less registers, and offers eight times higher throughput-rate than the existing similar structure. For the same block-size and filter-length, the proposed variable-coefficient structure involves 7.2 times more adders, the same number of registers, eight times more MUXes, and offers eight times higher throughput than the best available similar structure. Synthesis result shows that the proposed fixed-coefficient structure for block-size 8 and filter-length 32 involve 47% less area delay product (ADP) and 42% less energy per sample (EPS) than the existing structure and offers nearly eight times higher throughput than others. For the same block-size and filter-length, the proposed structure for variable-coefficient FIR involves 71% less ADP and 65% less EPS than the similar existing structures.

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